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XR-T5683AID 반도체 회로 부품 판매점

PCM Line Interface Chip



Exar Corporation 로고
Exar Corporation
XR-T5683AID 데이터시트, 핀배열, 회로
...the analog plus companyTM
XR-T5683A
PCM Line
Interface Chip
FEATURES
D Single 5V Supply
D Receiver Input Can Be Either Balanced or
Unbalanced
D Up To 8.448Mbps Operation In Both Tx and Rx
Directions
D TTL Compatible Interface
June 1997-3
D Device Can Be Used as a Line Interface Unit With-
out Clock Recovery
APPLICATIONS
D T1, T2, E1 & E2 Rates, PCM Line Interface
D Network Multiplexing and Terminating Equipment
GENERAL DESCRIPTION
The XR-T5683A is a PCM line interface chip consisting of
both transmit and receive circuitry. This device is offered
in a plastic dual in-line (PDIP) or in a surface mount
package (SOIC). The maximum bit rate of the chip is
8.448Mbps, and the signal level to the receiver can be
attenuated by -10dB cable loss at one-half the bit rate. At
nominal supply voltage operation, the typical current
consumption is 40mA.
ORDERING INFORMATION
Part No.
XR-T5683AIP
XR-T5683AID
Package
18 Lead 300 Mil PDIP
18 Lead 300 Mil JEDEC SOIC
Operating
Temperature Range
-40°C to +85°C
-40°C to +85°C
BLOCK DIAGRAM
RXDATA+ 2
RXDATA- 3
RVCC 9
RGND 7
TVCC 18
TPOS 17
TCLK 16
TNEG 12
TGND 14
Peak
Detector
BIAS
BIAS
1 PDC
Positive
Threshold
Comparator
Negative
Threshold
Comparator
Open Collector
Driver
Open Collector
Driver
Figure 1. Block Diagram
TTL Buffer
11 RPOS
TTL Buffer
TTL Buffer
8 RCLK
4 TE
10 RNEG
6 TANK BIAS
5 BIAS
13 TXDATA+
15 TXDATA-
Rev. 2.01
E1995
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017
1


XR-T5683AID 데이터시트, 핀배열, 회로
XR-T5683A
PIN CONFIGURATION
PDC
RXDATA+
RXDATA-
TE
BIAS
TANK BIAS
RGND
RCLK
RVCC
1
2
3
4
5
6
7
8
9
18 TVCC
17 TPOS
16 TCLK
15 TXDATA-
14 TGND
13 TXDATA+
12 TNEG
11 RPOS
10 RNEG
18 Lead PDIP (0.300”)
PDC
RXDATA+
RXDATA-
TE
BIAS
TANK BIAS
RGND
RCLK
RVCC
1 18
2 17
3 16
4 15
5 14
6 13
7 12
8 11
9 10
TVCC
TPOS
TCLK
TXDATA-
TGND
TXDATA+
TNEG
RPOS
RNEG
18 Lead SOIC (JEDEC, 0.300”)
PIN DESCRIPTION
Pin #
1
2
3
4
5
6
7
Symbol
PDC
RXDATA+
RXDATA-
TE
BIAS
TANK BIAS
RGND
8 RCLK
9 RVCC
10 RNEG
11 RPOS
12 TNEG
13 TXDATA+
14 TGND
15 TXDATA-
16 TCLK
17 TPOS
18 TVCC
Type
I
I
O
O
O
O
O
O
I
O
O
I
I
Description
Peak Detector Capacitor. This pin should be connected to a 0.1µF capacitor.
Receive Analog Input Positive. Line analog input.
Receive Analog Input Negative. Line analog input.
Tank Excitation Output. This output connects to one side of the tank circuitry.
Bias. This output is to be connected to the center tap of the receive transformer.
Tank Bias. The tank circuitry is biased via this output.
Receiver Ground. To minimize ground interference a separate pin is used to ground the
receive section.
Recovered Receive Clock. Recovered clock signal to the terminal equipment.
Receive Supply Voltage. 5V supply voltage to the receive section.
Receive Negative Data. Negative pulse data output to the terminal equipment (active low).
Receive Positive Data. Positive pulse data output to the terminal equipment (active low).
Transmit Negative Data. TNEG is valid while TCLK is high.
Transmit Positive Output. Transmit bipolar signal is driven to the line via a transformer.
Transmit Ground.
Transmit Negative Output. Transmit bipolar signal is driven to the line via a transformer.
Transmit Clock. Timing element for TPOS and TNEG.
Transmit Positive Data. TPOS is valid while TCLK is high.
Transmit Supply Voltage. 5V supply voltage to the transmit section.
Rev. 2.01
2




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