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LB-9 반도체 회로 부품 판매점

Universal Balancing Techniques



National Semiconductor 로고
National Semiconductor
LB-9 데이터시트, 핀배열, 회로
Universal Balancing
Techniques
National Semiconductor
Linear Brief 9
August 1969
IC op amps are widely accepted as a universal analog
component. Although the circuit designs may vary, most
devices are functionally interchangeable. However, offset
voltage balancing remains a personality trait of the particular
amplifier design. The techniques shown here allow offset
voltage balancing without regard to the internal circuitry of
the amplifier.
00846002
R1 = 2000 R3 \ R4
R4 \ R3 10 k
00846001
FIGURE 1. Offset Voltage Adjustment for Inverting
Amplifiers Using 10 kSource Resistance or Less
The circuit shown in Figure 1 is used to balance out the
offset voltage of inverting amplifiers having a source resis-
tance of 10 kor less. A small current is injected into the
summing node of the amplifier through R1. Since R1 is 2000
times as large as the source resistance the voltage at the
arm of the pot is attenuated by a factor of 2000 at the
summing node. With the values given and ±15V supplies the
output may be zeroed for offset voltages up to ±7.5 mW.
If the value of the source resistance is much larger than 10
k, the resistance needed for R1 becomes too large. In this
case it is much easier to balance out the offset by supplying
a small voltage at the non-inverting input of the amplifier.
Figure 2 shows such a scheme. Resistors R1 and R2 divide
the voltage at the arm of the pot to supply a ±7.5 mW
adjustment range with ±15V supplies.
This adjustment method is also useful when the feedback
element is a capacitor or non-linear device.
FIGURE 2. Offset Voltage Adjustment for Inverting
Amplifiers Using Any Type of Feedback Element
This technique of supplying a small voltage effectively in
series with the input is also used for adjusting non-inverting
amplifiers. As is shown in Figure 3, divider R1, R2 reduces
the voltage at the arm of the pot to ±7.5 mW for offset
adjustment. Since R2 appears in series with R4, R2 should
be considered when calculating the gain. If R4 is greater than
10 kthe error due to R2 is less than 1%.
© 2002 National Semiconductor Corporation AN008460
www.national.com


LB-9 데이터시트, 핀배열, 회로
00846003
00846004
FIGURE 3. Offset Voltage Adjustment for
Non-Inverting Amplifiers
A voltage follower may be balanced by the technique shown
in Figure 4. R1 injects a current which produces a voltage
drop across R3 to cancel the offset voltage. The addition of
the adjustment resistors causes a gain error, increasing the
gain by 0.05%. This small error usually causes no problem.
The adjustment circuit essentially causes the offset voltage
to appear at full output, rather than at low output levels,
where it is a large percentage error.
FIGURE 4. Offset Voltage Adjustment for
Voltage Followers
Differential amplifiers are somewhat more difficult to bal-
ance. The offset adjustment used for a differential amplifier
can degrade the common mode rejection ratio. Figure 5
shows an adjustment circuit which has minimal effect on the
common mode rejection. The voltage at the arm of the pot is
divided by R4 and R5 to supply an offset correction of ±7.5
mV. R4 and R5 are chosen such that the common mode
rejection ratio is limited by the amplifer for values of R3
greater than 1 k. If R3 is less than 1k the shunting of R4 by
R5 must be considered when choosing the value of R3.
00846005
FIGURE 5. Offset Voltage Adjustment for
Differential Amplifiers
The techniques described for balancing offset voltage at the
input of the amplifier offer two main advantages: First, they
are universally applicable to all operational amplifiers and
allow device interchangeability with no modifications to the
balance circuitry. Second, they permit balancing without in-
terfering with the internal circuitry of the amplifier. The elec-
trical parameters of the amplifiers are tested and guaranteed
without balancing. Although it doesn’t usually happen, bal-
ancing could degrade performance.
www.national.com
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