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K9F2808U0A- 반도체 회로 부품 판매점

16M x 8 Bit NAND Flash Memory



Samsung semiconductor 로고
Samsung semiconductor
K9F2808U0A- 데이터시트, 핀배열, 회로
K9F2808U0A-YCB0, K9F2808U0A-YIB0
Document Title
16M x 8 Bit NAND Flash Memory
FLASH MEMORY
Revision History
Revision No. History
0.0 Initial issue.
Draft Date
April 10th 1999
0.1 1. Revised real-time map-out algorithm(refer to technical notes)
July 23th 1999
0.2 1. Changed device name
- KM29U128AT -> K9F2808U0A-YCB0
- KM29U128AIT -> K9F2808U0A-YIB0
Sep. 15th 1999
0.3 1. Changed sequential row read opera tion
Mar. 21th 2000
- The Sequential Read 1 and 2 operation is allowed only within a block
2. Changed invalid block(s) marking method prior to shipping
- The invalid block(s) information is written the 1st or 2nd page of the
invalid block(s) with 00h data
--->The invalid block(s) status is defined by the 6th byte in the spare
area. Samsung makes sure that either the 1st or 2nd page of every
invalid block has 00h data at the column address of 517.
0.4 1. Changed endurance : 1million -> 100K program/erase cycles
May 15th 2000
2. Changed invalid block(s) marking method prior to shipping
- The invalid block(s) status is defined by the 6th byte in the spare
area. Samsung makes sure that either the 1st or 2nd page of every
invalid block has 00h data at the column address of 517.
--->The invalid block(s) status is defined by the 6th byte in the spare
area. Samsung makes sure that either the 1st or 2nd page of every
invalid block has non-FFh data at the column address of 517.
0.5 1. Changed SE pin description
July 17th 2000
- SE is recommended to coupled to GND or Vcc and should not be
toggled during reading or programming.
0.6 1. Changed don’t care mode in address cycles
Nov. 20th 2000
- *X can be "High" or "Low" => *L must be set to "Low"
2. Explain how pointer operation works in detail.
3. Renamed GND input (pin # 6) on behalf of SE (pin # 6)
- The SE input controls the access of the spare area. When SE is high,
the spare area is not accessible for reading or programming. SE is rec
ommended to be coupled to GND or Vcc and should not be toggled
during reading or programming.
=> Connect this input pin to GND or set to static low state unless the
sequential read mode excluding spare area is used.
4. Updated operation for tRST timing
- If reset command(FFh) is written at Ready state, the device goes into
Busy for maximum 5us.
Remark
Advanced
Information
Preliminary
Preliminary
Final
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
1


K9F2808U0A- 데이터시트, 핀배열, 회로
K9F2808U0A-YCB0, K9F2808U0A-YIB0
FLASH MEMORY
16M x 8 Bit NAND Flash Memory
FEATURES
Voltage Supply : 2.7V~3.6V
Organization
- Memory Cell Array : (16M + 512K)bit x 8bit
- Data Register : (512 + 16)bit x8bit
Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase : (16K + 512)Byte
528-Byte Page Read Operation
- Random Access : 10µs(Max.)
- Serial Page Access : 50ns(Min.)
Fast Write Cycle Time
- Program Time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
Command/Address/Data Multiplexed I/O Port
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
Command Register Operation
Package : 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
GENERAL DESCRIPTION
The K9F2808U0A is a 16M(16,777,216)x8bit NAND Flash
Memory with a spare 512K(524,288)x8bit. Its NAND cell pro-
vides the most cost-effective solution for the solid state mass
storage market. A program operation programs the 528-byte
page in typically 200µs and an erase operation can be per-
formed in typically 2ms on a 16K-byte block. Data in the page
can be read out at 50ns cycle time per byte. The I/O pins serve
as the ports for address and data input/output as well as com-
mand inputs. The on-chip write controller automates all pro-
gram and erase functions including pulse repetition, where
required, and internal verify and margining of data. Even the
write-intensive systems can take advantage of the
K9F2808U0As extended reliability of 100K program/erase
cycles by providing ECC(Error Correcting Code) with real time
mapping-out algorithm.
The K9F2808U0A is an optimum solution for large nonvolatile
storage applications such as solid state file storage, digital
voice recorder, digital still camera and other portable applica-
tions requiring non-volatility.
PIN CONFIGURATION
N.C
N.C
N.C
N.C
N.C
SE
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
K9F2808U0A-YCB0/YIB0
PIN DESCRIPTION
48 N.C
47 N.C
46 N.C
45 N.C
44 I/O7
43 I/O6
42 I/O5
41 I/O4
40 N.C
39 N.C
38 N.C
37 Vcc
36 Vss
35 N.C
34 N.C
33 N.C
32 I/O3
31 I/O2
30 I/O1
29 I/O0
28 N.C
27 N.C
26 N.C
25 N.C
Pin Name
I/O0 ~ I/O7
CLE
ALE
CE
RE
WE
WP
GND
R/B
VCC
VSS
N.C
Pin Function
Data Input/Outputs
Command Latch Enable
Address Latch Enable
Chip Enable
Read Enable
Write Enable
Write Protect
GND input for enabling spare area
Ready/Busy output
Power
Ground
No Connection
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
2




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K9F2808U0A

16M x 8 Bit NAND Flash Memory - Samsung semiconductor



K9F2808U0A-

16M x 8 Bit NAND Flash Memory - Samsung semiconductor



K9F2808U0A-YCB0

16M x 8 Bit NAND Flash Memory - Samsung semiconductor



K9F2808U0A-YIB0

16M x 8 Bit NAND Flash Memory - Samsung semiconductor