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K6R1008C1B-C8 반도체 회로 부품 판매점

128Kx8 Bit High Speed Static RAM5V Operating/ Revolutionary Pin out. Operated at Commercial and Industrial Temperature Ranges.



Samsung semiconductor 로고
Samsung semiconductor
K6R1008C1B-C8 데이터시트, 핀배열, 회로
K6R1008C1B-C, K6R1008C1B-I
PRELIMINARY
PRPEreLlIiMmIiNnAarRyY
CMOS SRAM
Document Title
128Kx8 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out.
Operated at Commercial and Industrial Temperature Ranges.
Revision History
Rev No.
History
Rev. 0.0
Initial release with Design Target.
Rev.1.0
Release to Preliminary Data Sheet.
1.1. Replace Design Target to Preliminary.
Rev.2.0
Release to Final Data Sheet.
2.1. Delete Preliminary.
2.2. Delete 32-SOJ-300 package.
2.3. Delete L-version.
2.4. Delete Data Retention Characteristics and Waveform.
2.5. Add Capacitive load of the test environment in A.C test load.
2.6. Change D.C characteristics.
Items
Previous spec.
(8/10/12ns part)
Changed spec.
(8/10/12ns part)
ICC
160/150/140mA
160/155/150mA
ISB
30mA
50mA
Draft Data
Apr. 1st, 1997
Jun. 1st, 1997
Remark
Design Target
Preliminary
Feb. 25th, 1998 Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 2.0
February 1998


K6R1008C1B-C8 데이터시트, 핀배열, 회로
K6R1008C1B-C, K6R1008C1B-I
PRELIMINARY
PRPEreLlIiMmIiNnAarRyY
CMOS SRAM
128K x 8 Bit High-Speed CMOS Static RAM
FEATURES
• Fast Access Time 8,10,12ns(Max.)
• Low Power Dissipation
Standby (TTL) : 50mA(Max.)
(CMOS) : 10mA(Max.)
Operating K6R1008C1B-8 : 160mA(Max.)
K6R1008C1B-10 : 155mA(Max.)
K6R1008C1B-12 : 150mA(Max.)
• Single 5.0V ±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
K6R1008C1B-J : 32-SOJ-400
K6R1008C1B-T: 32-TSOP2-400CF
GENERAL DESCRIPTION
The K6R1008C1B is a 1,048,576-bit high-speed Static Random
Access Memory organized as 131,072 words by 8 bits. The
K6R1008C1B uses 8 common input and output lines and has
an output enable pin which operates faster than address
access time at read cycle. The device is fabricated using SAM-
SUNGs advanced CMOS process and designed for high-
speed circuit technology. It is particularly well suited for use in
high-density high-speed system applications. The
K6R1008C1B is packaged in a 400mil 32-pin plastic SOJ or
TSOP2 forward.
ORDERING INFORMATION
K6R1008C1B-C8/C10/C12
K6R1008C1B-I8/I10/I12
Commercial Temp.
Industrial Temp.
PIN CONFIGURATION(Top View)
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
Pre-Charge Circuit
A0
A1
A2
A3 Memory Array
A4
256 Rows
512x8 Columns
A5
A6
A7
I/O1~I/O8
Data
Cont.
I/O Circuit
Column Select
CLK
Gen.
A8 A9 A10 A11 A12 A13 A14 A15 A16
CS
WE
OE
A0 1
A1 2
A2 3
A3 4
CS 5
I/O1 6
I/O2 7
Vcc 8
Vss 9
I/O3 10
I/O4 11
WE 12
A4 13
A5 14
A6 15
A7 16
SOJ/
TSOP2
32 A16
31 A15
30 A14
29 A13
28 OE
27 I/O8
26 I/O7
25 Vss
24 Vcc
23 I/O6
22 I/O5
21 A12
20 A11
19 A10
18 A9
17 A8
PIN FUNCTION
Pin Name
A0 - A16
WE
CS
OE
I/O1 ~ I/O8
VCC
VSS
N.C
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power(+5.0V)
Ground
No Connection
-2-
Rev 2.0
February 1998




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