JLC1562BFEL 반도체 회로 부품 판매점
I2C Bus I/O Expander
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 ON Semiconductor |
JLC1562B
I2C Bus I/O Expander
The JLC1562B facilitates easy I2C Bus expandibility. Multiple
devices (up to 8 on the same I2C Bus) are easily added as each device
has its own selectable 3−bit address. The JLC1562B provides an 8−bit
bidirectional input/output port and 6−bit resolution Digital to Analog
Converter. The voltage on pins P0−P4 is compared with a controllable
threshold voltage and the results are readable through the I2C Bus.
I2C Bus interface pins SDA, SCL and A0−A2 are; Serial Data,
Serial Clock and Device Address respectively. External interface pins
are P0−P7 and VDAC; I/O Port and D/A output.
Features
• Pb−Free Packages are Available*
• Low Power Dissipation
• I2C−Bus Format (2−Wire Type; SDA, SCL) Data Transfer
• 6−bit DAC
• Bus Address Selectable (3−bit)
• Address Input Pins are Pulled Up to VDD with Internal Resistor
• I/O Pins are Open Drain Outputs
• 5 Comparators at Inputs
• Inputs Protected from External Bus Currents in Power Down Mode
A0 1
A1 2
A2 3
P0 4
P1 5
P2 6
P3 7
VSS 8
16 VDD
15 SDA
14 SCL
13 VDAC
12 P7
11 P6
10 P5
9 P4
Figure 1. Pin Assignment
A0−A2
P0−P4
P5−P7
SCL
SDA
VDAC
PIN LIST
Chip Address Input
Comparator Input / Open Drain Output
Comparator Input / Open Drain Output
Serial Clock Input
I2C Data Output
DAC Output
http://onsemi.com
PDIP−16
N SUFFIX
CASE 648
EIAJ−16
F SUFFIX
CASE 966
MARKING
DIAGRAMS
16
JLC1562BN
AWLYYWW
1
16
JLC1562B
ALYW
1
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
ORDERING INFORMATION
Device
Package
Shipping†
JLC1562BN
PDIP−16
500 / Unit PAK
JLC1562BNG
PDIP−16
(Pb−Free)
500 / Unit PAK
JLC1562BF
JLC1562BFEL
EIAJ−16
(Pb−Free)
EIAJ−16
(Pb−Free)
50 Units / Rail
2000 Units / Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2004
July, 2004 − Rev. 4
1
Publication Order Number:
JLC1562B/D
JLC1562B
Power−On
Reset
SDA
SCL
VDD
8 Bit
6 Bit
Latch
6−Bit
DAC
P7
P6
P5
P4
P3
P2
P1
P0
A0
A1 1/2 VCC
A2 3 Bit Comp.
(C5−C7) A
5 Bit
5 Bit Comp.
(C0−C4) B
NOTE: Internal Power On Reset sets P0 ~ P7 low, sets VDAC to 1/80 VDD
and selects 1/2 VDD for Comparator “B” threshold.
Figure 2. Block Diagram
VDD
16 X R65
R64
Pin 1
VDAC
Comparator “B”
Vref
R63
R40
R39
R2
R1
GND
6:64 De−MUX (1 of 64 Decoder)
Bits D0 − D5 of Write Data (2)
Vref Selector
Bit D6 of Write Data (2)
Write Data (2)
D6
1
0
Vref Value
Vref = VDAC
Vref
+
40
80
VDD
Write Data (2)
D5 D4 D3 D2 D1 D0
111111
•
•
•
•
1LSB +
1
80
VDD
0
0
0
0
0
1
000000
Vref
64
80
VDD
•
•
•
•
2
80
VDD
1
80
VDD
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