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PDF 74221 Data sheet ( Hoja de datos )
| Número de pieza | 74221 | |
| Descripción | Dual Non-Retriggerable Monostable Multivibrator | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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September 1983
Revised February 1999
MM74HC221A
Dual Non-Retriggerable Monostable Multivibrator
General Description
The MM74HC221A high speed monostable multivibrators
(one shots) utilize advanced silicon-gate CMOS technol-
ogy. They feature speeds comparable to low power Schot-
tky TTL circuitry while retaining the low power and high
noise immunity characteristic of CMOS circuits.
Each multivibrator features both a negative, A, and a posi-
tive, B, transition triggered input, either of which can be
used as an inhibit input. Also included is a clear input that
when taken low resets the one shot. The MM74HC221A
can be triggered on the positive transition of the clear while
A is held LOW and B is held HIGH.
The MM74HC221A is a non-retriggerable, and therefore
cannot be retriggered until the output pulse times out.
Pulse width stability over a wide range of temperature and
supply is achieved using linear CMOS techniques. The out-
put pulse equation is simply: PW = (REXT) (CEXT); where
PW
is in seconds, R is in ohms, and C is in farads. All inputs
are protected from damage due to static discharge by
diodes to VCC and ground.
Features
s Typical propagation delay: 40 ns
s Wide power supply range: 2V–6V
s Low quiescent current: 80 µA maximum (74HC Series)
s Low input current: 1 µA maximum
s Fanout of 10 LS-TTL loads
s Simple pulse width formula T = RC
s Wide pulse range: 400 ns to ∞ (typ)
s Part to part variation: ±5% (typ)
s Schmitt Trigger A & B inputs enable infinite signal input
rise or fall times
Ordering Code:
Order Number Package Number
Package Description
MM74HC221AM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC221ASJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC221AMTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC221AN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Timing Component
Top View
Note: Pin 6 and Pin 14 must be hard-wired to GND.
© 1999 Fairchild Semiconductor Corporation DS005325.prf
www.fairchildsemi.com
1 page  
Theory of Operation
FIGURE 1.
TRIGGER OPERATION
As shown in Figure 1 and the logic diagram before an input
trigger occurs, the monostable is in the quiescent state with
the Q output LOW, and the timing capacitor CEXT com-
pletely charged to VCC. When the trigger input A goes from
VCC to GND (while inputs B and clear are held to VCC) a
valid trigger is recognized, which turns on comparator C1
and N-channel transistor N11. At the same time the output
latch is set. With transistor N1 on, the capacitor CEXT rap-
idly discharges toward GND until VREF1 is reached. At this
point the output of comparator C1 changes state and tran-
sistor N1 turns off. Comparator C1 then turns off while at
the same time comparator C2 turns on. With transistor N1
off, the capacitor CEXT begins to charge through the timing
resistor, REXT, toward VCC. When the voltage across CEXT
equals VREF2, comparator C2 changes state causing the
output latch to reset (Q goes LOW) while at the same time
disabling comparator C2. This ends the timing cycle with
the monostable in the quiescent state, waiting for the next
trigger.
A valid trigger is also recognized when trigger input B goes
from GND to VCC (while input A is at GND and input clear
is at VCC2). The MM74HC221 can also be triggered when
clear goes from GND to VCC (while A is at Gnd and B is at
VCC6).
It should be noted that in the quiescent state CEXTis fully
charged to VCC causing the current through resistor REXT
to be zero. Both comparators are “off” with the total device
current due only to reverse junction leakages. An added
feature of the MM74HC221 is that the output latch is set via
the input trigger without regard to the capacitor voltage.
Thus, propagation delay from trigger to Q is independent of
the value of CEXT, REXT, or the duty cycle of the input
waveform.
The MM74HC221 is non-retriggerable and will ignore input
transitions on A and B until it has timed out 3 and 4.
RESET OPERATION
These one shots may be reset during the generation of the
output pulse. In the reset mode of operation, an input pulse
on clear sets the reset latch and causes the capacitor to be
fast charged to VCC by turning on transistor Q1 5. When
the voltage on the capacitor reaches VREF2, the reset latch
will clear and then be ready to accept another pulse. If the
clear input is held LOW, any trigger inputs that occur will be
inhibited and the Q and Q outputs of the output latch will
not change. Since the Q output is reset when an input low
level is detected on the Clear input, the output pulse T can
be made significantly shorter than the minimum pulse width
specification.
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| PDF Descargar | [ Datasheet 74221.PDF ] | |
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