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68901N04 반도체 회로 부품 판매점

MULTI.FUNCTION PERIPHERAL



STMicroelectronics 로고
STMicroelectronics
68901N04 데이터시트, 핀배열, 회로
MK68901
MULTI–FUNCTION PERIPHERAL
. 8 INPUT/OUTPUT PINS
Individually programmable direction
. Individual interrupt source capability
- Programmable edge selection
16 SOURCE INTERRUPT CONTROLLER
8 Internal sources
8 External sources
Individual source enable
Individual source masking
Programmable interrupt service modes
- Polling
- Vector generation
. - Optional In-service status
Daisy chaining capability
FOUR TIMERS WITH INDIVIDUALLY PRO-
GRAMMABLE PRESCALING
Two multimode timers
- Delay mode
- Pulse width measurement mode
- Event counter mode
Two delay mode timers
. Independent clock input
Time out output option
SINGLE CHANNEL USART
Full Duplex
Asynchronous to 65 kbps
Byte synchronous to 1 Mbps
Internal/External baud rate generation
DMA handshake signals
.. Modem control
Loop back mode
68000 BUS COMPATIBLE
48 PIN DIP OR 52 PIN PLCC
1
DPIP48
Figure 1 : Pin connections.
PLCC52
DESCRIPTION
The MK68901 MFP (Multi-Function Peripheral) is a
combination of many of the necessary peripheral
functions in a microprocessor system.
Included are :
Eight parallel I/O lines
Interrrupt controller for 16 sources
Four timers
Single channel full duplex USART
The use of the MFP in a system can significantly re-
duce chip count, thereby reducing system cost. The
MFP is completely 68000 bus compatible, and 24 di-
rectly addressable internal registers provide the ne-
MFP
December 1988
1/33


68901N04 데이터시트, 핀배열, 회로
MK68901
necessary control and status interface to the pro-
grammer.
The MFP is a derivative of the MK3801 STI, a Z80
family peripheral.
PIN DESCRIPTION
GND : Ground
VCC : +5 volts (± 5%)
CS : Chip Select (input, active, low). CS is u-
sed to select the MK68901 MFP for ac-
cesses to the internal registers. CS and
IACK must not be asserted at the same
time.
DS : Data Strobe (input, active low). DS is u-
sed as part of the chip select and interrupt
acknowledge functions.
R/W :
Read/Write (input). R/W is the signal
from the bus master indicating whether
the current bus cycle is a Read (High) or
Write (Low) cycle.
DTACK : Data Transfer Acknowledge. (output, ac-
tive low, tri-stateable) DTACK is used to
signal the bus master that data is ready,
or that data has been accepted by the
MK68901 MFP.
A1-A5 : Address Bus (inputs). The adress bus is
used to adress one of the internal regis-
ters during a read or write cycle.
D0-D7 :
Data Bus (bi-directional, tri-stateable).
The data bus is used to receive data from
or transmit data to one of the internal re-
gisters during a read or write cycle. It is
also used to pass a vector during an in-
terrupt acknowledge cycle.
CLK :
Clock (input). This input is used to pro-
vide the internal timing for the MK68901
MFP.
RESET : Device reset. (input, active low). Reset
disables the USART receiver and trans-
mitter, stops all timers and forces the ti-
mer outputs low, disables all interrupt
channels and clears any pending inter-
rupts. The General Purpose Interrupt/I/O
lines will be placed in the tri-state input
mode. All internal registers (except the ti-
mer, USART data registers, and transmit
status register) will be cleared.
INTR :
Interrupt Request (output, active low, o-
pen drain). INTR is asserted when the
MK68901 MFP is requesting an interrupt.
INTR is negated during an interrupt ac-
2/33
knowledge cycle or by clearing the pen-
ding interrupt(s) through software.
IACK :
Interrupt Acknowledge (input, active
low). IACK is used to signal the MK68901
MFP that the CPU is acknowledging an
interrupt. CS and IACk must not be as-
serted at the same time.
IEI : Interrupt Enable In (input, active low). IEI
is used to signal the MK68901 MFP that
no higher priority device is requesting in-
terrupt service.
IEO :
Interrupt Enable Out (output, active low).
IEO is used to signal lower priority peri-
pherals that neither the MK68901 MFP
nor another higher priority peripheral is
requesting interrupt service.
10-17 :
General Purpose Interrupt I/O lines.
These lines may be used as interrupt in-
puts and/or I/O lines. When used as in-
terrupt inputs, their active edge is pro-
grammable. A data direction register is u-
sed to define which lines are to be Hi-Z
inputs and which lines are to be push-pull
TTL compatible outputs.
SO : Serial Output. This is the output of the U-
SART transmitter.
SI : Serial Input. This is the input to the U-
SART receiver.
RC : Receiver Clock. This input controls the
serial bit rate of the USART receiver.
TC : Transmitter Clock. This input controls the
serial bit rate of the USART transmitter.
RR : Receiver Ready. (output, active low)
DMA output for receiver, which reflects
the status of Buffer Full in port number
15.
TR : Transmitter Ready. (output, active low)
DMA output for transmitter, which re-
flects the status of Buffer Empty in port
number 16.
TAO,TBO, Timer Outputs. Each of the four timers
TCO,TDO:has an output which can produce a
square wave. The output will change
states each timer cycle ; thus one full pe-
riod of the timer out signal is equal to two
timer cycles. TAO or TBO can be reset
(logic ”O”) by a write to TACR, or TBCR
respectively.
XTAL1,
XTAL2 :
Timer Clock inputs. A crystal can be
connected between XTAL1 and XTAL2,
or XTAL1 can be driven with a TTL level
clock. When driving XTAL1 with a TTL le-




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