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PDF 74AC521SJ Data sheet ( Hoja de datos )
| Número de pieza | 74AC521SJ | |
| Descripción | 8-Bit Identity Comparator | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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November 1988
Revised March 2005
74AC521 • 74ACT521
8-Bit Identity Comparator
General Description
The AC/ACT521 is an expandable 8-bit comparator. It com-
pares two words of up to eight bits each and provides a
LOW output when the two words match bit for bit. The
expansion input IA B also serves as an active LOW enable
input.
Features
s ICC reduced by 50%
s Compares two 8-bit words in 6.5 ns typ
s Expandable to any word length
s 20-pin package
s Outputs source/sink 24 mA
s ACT521 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC521SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74AC521SJ
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC521MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC521PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT521SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ACT521SJ
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT521MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT521PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering table.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
A0–A7
B0–B7
TA B
OA B
Description
Word A Inputs
Word B Inputs
Expansion or Enable Input
Identity Output
FACT¥ is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation DS009964
www.fairchildsemi.com
1 page  
AC Electrical Characteristics for ACT
Symbol
Parameter
tPLH Propagation Delay
An or Bn to OA B
tPHL Propagation Delay
An or Bn to OA B
tPLH Propagation Delay
IA B to OA B
tPHL Propagation Delay
IA B to OA B
Note 9: Voltage Range 5.0 is 5.0V r 0.5V
VCC
(V)
(Note 9)
5.0
5.0
5.0
5.0
Min
3.0
3.0
2.0
2.5
Capacitance
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
40
TA 25qC
CL 50 pF
Typ
5.5
Max
9.0
TA 40qC to 85qC
CL 50 pF
Min Max
2.5 9.5
6.0 10.0 2.5 11.0
4.0 6.5 2.0 7.0
5.0 7.5 2.0 8.0
Units
pF
pF
Conditions
VCC OPEN
VCC 5.0V
Units
ns
ns
ns
ns
5 www.fairchildsemi.com
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| PDF Descargar | [ Datasheet 74AC521SJ.PDF ] | |
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