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Fairchild Semiconductor |
February 1989
Revised November 1999
74AC520 • 74ACT520
8-Bit Identity Comparator
General Description
The AC/ACT520 are expandable 8-bit comparators. They
compare two words of up to eight bits each and provide a
LOW output when the two words match bit for bit. The
expansion input IA = B also serves as an active LOW enable
input.
Features
s Compares two 8-bit words in 6.5 ns typ
s Expandable to any word length
s 20-pin package
s Outputs source/sink 24 mA
s ACT520 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC520SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74AC520PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT520SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACT520SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT520PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
A0–A7
B0–B7
TA = B
OA = B
Description
Word A Inputs
Word B Inputs
Expansion or Enable Input
Identity Output
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010194
www.fairchildsemi.com
Truth Table
Inputs
IA = B
A, B
L A = B (Note 1)
L A≠Β
H A = B (Note 1)
H A≠Β
H = HIGH Voltage Level
L = LOW Voltage Level
Note 1: *A0 = B0, A1 = B1, A2 = B2, etc.
Outputs
OA = B
L
H
H
H
Logic Diagram
Applications
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Ripple Expansion
Parallel Expansion
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