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STMicroelectronics |
74AC174
HEX D-TYPE FLIP FLOP WITH CLEAR
PRELIMINARY DATA
s HIGH SPEED:
fMAX =125 MHz (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 8 µA (MAX.) at TA = 25 oC
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
s 50Ω TRANSMISSION LINE DRIVING
B
(Plastic Package)
M
(Micro Package)
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24 mA (MIN)
s BALANCED PROPAGATION DELAYS:
ORDER CODES :
74AC174B
74AC174M
TTL.
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 174
s IMPROVED LATCH-UP IMMUNITY
Information signals applied to D inputs are
transfered to the Q output on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independentelyof the other inputs .
All inputs and outputs are equipped with
DESCRIPTION
protection circuits against static discharge, giving
The AC174 is an high-speed CMOS HEX themwww.DataSheet4U.com 2KV ESD immunity and transient excess
D-TYPE FLIP FLOP WITH CLEAR fabricated voltage.
with sub-micron silicon gate and double-layer
metal wiring C2MOS technology. It is ideal for low
power applications mantaining high speed
operation similar to eqivalent Bipolar Schottky
PIN CONNECTION AND IEC LOGIC SYMBOLS
May 1997
1/10
74AC174
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1
2, 5, 7, 10,
12, 15
3, 4, 6, 11,
13, 14
9
8
16
SYMBOL
CLEAR
Q0 to Q5
NAME AND FUNCTION
Asyncronous Master Reset
(Active LOW)
Flip-Flop Outpus
D0 to D5 Data Inputs
CLOCK
GND
VCC
Clock Input (LOW-to-HIGH,
Edge- Triggered)
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
CLEAR
L
H
H
H
X: Don’t Care
INPUTS
D
X
L
H
X
LOGIC DIAGRAM
CLOCK
X
OUTPUTS
Q
L
L
H
Qn
FUNCTION
CLEAR
NO CHANGE
This logic diagram has not be used to estimate propagation delays
2/10
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