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Fairchild Semiconductor |
November 1988
Revised November 1999
74AC169
4-Stage Synchronous Bidirectional Counter
General Description
The AC169 is fully synchronous 4-stage up/down counter.
The AC169 is a modulo-16 binary counter. It features a
preset capability for programmable operation, carry looka-
head for easy cascading and a U/D input to control the
direction of counting. All state changes, whether in count-
ing or parallel loading, are initiated by the LOW-to-HIGH
transition of the Clock.
Features
s ICC reduced by 50%
s Synchronous counting and loading
s Built-In lookahead carry capability
s Presettable for programmable operation
s Outputs source/sink 24 mA
Ordering Code:
Order Number
74AC169SC
74AC169SJ
74AC169MTC
74AC169PC
Package Number
Package Description
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
www.DataSheet4U.com
IEEE/IEC
Pin Descriptions
Pin Names
CEP
CET
CP
P0–P3
PE
U/D
Q0–Q3
TC
Description
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input
Parallel Data Inputs
Parallel Enable Input
Up-Down Count Control Input
Flip-Flop Outputs
Terminal Count Output
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS009934
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Functional Description
The AC169 uses edge-triggered J-K-type flip-flops and
have no constraints on changing the control or data input
signals in either state of the Clock. The only requirement is
that the various inputs attain the desired state at least a
setup time before the rising edge of the clock and remain
valid for the recommended hold time thereafter. The paral-
lel load operation takes precedence over the other opera-
tions, as indicated in the Mode Select Table. When PE is
LOW, the data on the P0–P3 inputs enters the flip-flops on
the next rising edge of the Clock. In order for counting to
occur, both CEP and CET must be LOW and PE must be
HIGH; the U/D input then determines the direction of count-
ing. The Terminal Count (TC) output is normally HIGH and
goes LOW, provided that CET is LOW, when a counter
reaches zero in the Count Down mode or reaches 15 in the
Count Up mode. The TC output state is not a function of
the Count Enable Parallel (CEP) input level. If an illegal
state occurs, the AC169 will return to the legitimate
sequence within two counts. Since the TC signal is derived
by decoding the flip-flop states, there exists the possibility
of decoding spikes on TC. For this reason the use of TC as
a clock signal is not recommended (see logic equations
below).
1. Count Enable = CEP •CET • PE
2. Up: TC = Q0•Q1•Q 2Q3•(Up)•CET
3. Down: TC = Q0• Q1•Q2•Q3 •(Down)•CET
Mode Select Table
PE CEP CET
LX X
HL
L
HL
L
HH
X
HX
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Action on Rising
U/D
Clock Edge
X Load (Pn to Qn)
H Count Up (Increment)
L Count Down (Decrement)
X No Change (Hold)
X No Change (Hold)
State Diagram
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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