74F169PC 반도체 회로 부품 판매점
4-Stage Synchronous Bidirectional Counter
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 Fairchild Semiconductor |
April 1988
Revised July 1999
74F169
4-Stage Synchronous Bidirectional Counter
General Description
The 74F169 is a fully synchronous 4-stage up/down
counter. The 74F169 is a modulo-16 binary counter. Fea-
tures a preset capability for programmable operation, carry
lookahead for easy cascading and a U/D input to control
the direction of counting. All state changes, whether in
counting or parallel loading, are initiated by the LOW-to-
HIGH transition of the clock.
Features
s Asynchronous counting and loading
s Built-in lookahead carry capability
s Presettable for programmable operation
Ordering Code:
Order Number Package Number
Package Description
74F169SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F169SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F169PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009488
www.fairchildsemi.com
Unit Loading/Fan Out
Pin Names
Description
CEP
CET
CP
P0–P3
PE
U/D
Q0–Q3
TC
Count Enable Parallel Input (Active LOW)
Count Enable Trickle Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Parallel Data Inputs
Parallel Enable Input (Active LOW)
Up-Down Count Control Input
Flip-Flop Outputs
Terminal Count Output (Active LOW)
U.L.
HIGH/LOW
1.0/1.0
1.0/2.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
50/33.3
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
20 µA/−1.2 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−1 mA/20 mA
−1 mA/20 mA
Functional Description
The 74F169 uses edge-triggered J-K type flip-flops and
has no constraints on changing the control or data input
signals in either state of the clock. The only requirement is
that the various inputs attain the desired state at least a
setup time before the rising edge of the clock and remain
valid for the recommended hold time thereafter. The paral-
lel load operation takes precedence over other operations,
as indicated in the Mode Select Table. When PE is LOW,
the data on the P0–P3 inputs enters the flip-flops on the
next rising edge of the clock. In order for counting to occur,
both CEP and CET must be LOW and PE must be HIGH;
the U/D input then determines the direction of counting.
The Terminal Count (TC) output is normally HIGH and goes
LOW, provided that CET is LOW, when a counter reaches
zero in the Count Down mode or reaches 15 for the
74F169 in the Count Up mode. The TC output state is not a
function of the Count Enable Parallel (CEP) input level.
Since the TC signal is derived by decoding the flip-flop
states, there exists the possibility of decoding spikes on
TC. For this reason the use of TC as a clock signal is not
recommended (see logic equations below).
1. Count Enable = CEP • CET • PE
2. Up: (74F169): TC = Q0 • Q1 • Q2 • Q3 • (Up) • CET
3. Down: TC = Q0 • Q1 • Q2 • Q3 • (Down) • CET
Mode Select Table
PE CEP CET U/D
LXX
HL L
HL L
HHX
HXH
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
X
H
L
X
X
State Diagram
Action on Rising
Clock Edge
Load (Pn → Qn)
Count Up (Increment)
Count Down (Decrement)
No Change (Hold)
No Change (Hold)
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