74F161A 판매점 - 4-bit binary counter

Philips Semiconductors

4-bit binary counters

Product specification

74F161A, 74F163A

FEATURES

• Synchronous counting and loading

• Two count enable inputs for n-bit cascading

• Positive edge-triggered clock

• Asynchronous Master Reset (74F161A)

• Synchronous Reset (74F163A)

• High speed synchronous expansion

• Typical count rate of 130MHz

• Industrial range (–40°C to +85°C) available

DESCRIPTION

4-bit binary counters feature an internal carry look-ahead and can be

used for high-speed counting. Synchronous operation is provided by

having all flip-flops clocked simultaneously on the positive-going

edge of the clock. The clock input is buffered.

The outputs of the counters may be preset to High or Low level. A

Low level at the Parallel Enable (PE) input disables the counting

action and causes the data at the D0–D3 inputs to be loaded into

the counter on the positive-going edge of the clock (provided that

the setup and hold requirements for PE are met). Preset takes place

regardless of the levels at Count Enable (CEP, CET) inputs.

A Low level at the Master Reset (MR) input sets all the four outputs

of the flip-flops (Q0 – Q3) in 74F161A to Low levels, regardless of

the levels at CP, PE, CET and CEP inputs (thus providing an

asynchronous clear function). For the 74F163A, the clear function is

synchronous. A Low level at the Synchronous Reset (SR) input sets

all four outputs of the flip-flops (Q0 – Q3) to Low levels after the next

positive-going transition on the clock (CP) input (provided that the

setup and hold time requirements for SR are met). This action

occurs regardless of the levels at PE, CET, and CEP inputs. The

synchronous reset feature enables the designer to modify the

maximum count with only one external NAND gate (see Figure 1).

The carry look-ahead simplifies serial cascading of the counters.

Both Count Enable (CEP and CET) inputs must be High to count.

The CET input is fed forward to enable the TC output. The TC

output thus enabled will produce a High output pulse of a duration

approximately equal to the High level output of Q0. This pulse can

be used to enable the next cascaded stage (see Figure 2). The TC

output is subjected to decoding spikes due to internal race

conditions. Therefore, it is not recommended for use as clock or

asynchronous reset for flip-flops, registers, or counters.

TYPE

74F161A

74F163A

TYPICAL

fMAX

130MHz

TYPICAL SUPPLY CURRENT

(TOTAL)

46mA

ORDERING INFORMATION

DESCRIPTION

16-pin plastic DIP

ORDER CODE

COMMERCIAL RANGE

VCC = 5V ±10%, Tamb = 0°C to +70°C

N74F161AN, N74F163AN

INDUSTRIAL RANGE

VCC = 5V ±10%, Tamb = –40°C to +85°C

I74F161AN, I74F163AN

16-pin plastic SO

N74F161AD, N74F163AD

I74F161AD, I74F163AD

DRAWING

NUMBER

SOT38-4

SOT109-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F (U.L.) HIGH/LOW

D0 – D3

Data inputs

1.0/1.0

CEP

Count Enable Parallel input

1.0/1.0

CET

Count Enable Trickle input

1.0/2.0

CP Clock input (active rising edge)

1.0/1.0

PE Parallel Enable input (active Low)

1.0/2.0

MR Asynchronous Master Reset input

(active Low) for 74F161A

1.0/1.0

SR Synchronous Reset input

(active Low) for 74F163A

1.0/1.0

TC Terminal count output

50/33

Q0 – Q3

Flip-flop outputs

50/33

NOTE:

One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.

LOAD VALUE HIGH/LOW

20µA/0.6mA

20µA/1.2mA

20µA/0.6mA

20µA/1.2mA

20µA/0.6mA

1.0mA/20mA

1996 Jan 29

2 853–0347 16300

74F161A 반도체 회로 부품 판매점

4-bit binary counter

국내 전력반도체 판매점

일반적인 전자부품 판매점

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