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Fairchild Semiconductor |
April 1988
Revised July 1999
74F160A • 74F162A
Synchronous Presettable BCD Decade Counter
General Description
The 74F160A and 74F162A are high-speed synchronous
decade counters operating in the BCD (8421) sequence.
They are synchronously presettable for applications in pro-
grammable dividers. There are two types of Count Enable
inputs plus a Terminal Count output for versatility in forming
synchronous multistage counters. The F160A has an asyn-
chronous Master Reset input that overrides all other inputs
and forces the outputs LOW. The F162A has a Synchro-
nous Reset input that overrides counting and parallel load-
ing and allows all outputs to be simultaneously reset on the
rising edge of the clock. The F160A and F162A are high
speed versions of the F160 and F162.
Features
s Synchronous counting and loading
s High-speed synchronous expansion
s Typical count rate of 120 MHz
Ordering Code:
Order Number Package Number
Package Description
74F160ASC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F160ASJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F160APC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74F162ASC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F162APC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
74F160A
74F162A
© 1999 Fairchild Semiconductor Corporation DS009485
www.fairchildsemi.com
Logic Symbols
74F160A
IEEE/IEC
74F162A
74F160A
Unit Loading/Fan Out
74F162A
Pin Names
Description
U.L.
Input IIH/IIL
HIGH/LOW Output IOH/IOL
CEP
Count Enable Parallel Input
1.0/1.0 20 µA/−0.6 mA
CET
Count Enable Trickle Input
1.0/2.0 20 µA/−1.2 mA
CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA
MR (74F160A) Asynchronous Master Reset Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA
SR (74F162A) Synchronous Reset Input (Active LOW)
1.0/2.0 20 µA/−1.2 mA
P0–P3
PE
Parallel Data Inputs
Parallel Enable Input (Active LOW)
1.0/1.0
1.0/2.0
20 µA/−0.6 mA
20 µA/−1.2 mA
Q0–Q3
TC
Flip-Flop Outputs
Terminal Count Output
50/33.3
50/33.3
−1 mA/20 mA
−1 mA/20 mA
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