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74F132PC 반도체 회로 부품 판매점

Quad 2-Input NAND Schmitt Trigger



National Semiconductor 로고
National Semiconductor
74F132PC 데이터시트, 핀배열, 회로
November 1994
54F/74F132
Quad 2-Input NAND Schmitt Trigger
General Description
The ’F132 contains four 2-input NAND gates which accept
standard TTL input signals and provide standard TTL output
levels. They are capable of transforming slowly changing in-
put signals into sharply defined, jitter-free output signals. In
addition, they have a greater noise margin than conventional
NAND gates.
Each circuit contains a 2-input Schmitt trigger followed by
level shifting circuitry and a standard FAST® output struc-
ture. The Schmitt trigger uses positive feedback to effectively
speed-up slow input transitions, and provide different input
threshold voltages for positive and negative-going transi-
tions. This hysteresis between the positive-going and
negative-going input threshold (typically 800 mV) is deter-
mined by resistor ratios and is essentially insensitive to tem-
perature and supply voltage variations.
Features
n Guaranteed 4000V minimum ESD protection
n Standard Military Drawing (SMD)
n 5962-89487
Ordering Code: See Section 0
Commercial
74F132PC
74F132SC (Note 1)
74F132SJ (Note 1)
Military
54F132DM (Note 2)
54F132FM (Note 2)
54F132LM (Note 2)
Package
Number
N14A
J14A
M14A
M14D
W14B
E20A
Package Description
14-Lead (0.300" Wide) Molded Dual-In-Line
14-Lead Ceramic Dual-In-Line
14-Lead (0.150" Wide) Molded Small Outline, JEDEC
14-Lead (0.300" Wide) Molded Small Outline, EIAJ
14-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier, Type C
Note 1: Devices also available in 13" reel. Use suffix = SCX and SJX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix = DMQB, FMQB and LMQB.
Logic Symbol
IEEE/IEC
DSXXX
DS009477-3
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1997 National Semiconductor Corporation DS009477
PrintDate=1997/08/28 PrintTime=12:25:28 10193 ds009477 Rev. No. 1 cmserv Proof
www.national.com
1
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74F132PC 데이터시트, 핀배열, 회로
Connection Diagrams
Pin Assignment for
DIP, SOIC and Flatpak
Pin Assignment
for LCC
DS009477-1
Unit Loading/Fan Out See Section 0 for U.L. definitions
Pin Names
Description
An, Bn
On
Inputs
Outputs
U.L.
HIGH/LOW
1.0/1.0
50/33.3
54F/74F
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
−1 mA/20 mA
Function Table
Inputs
AB
LL
LH
HL
HH
H = HIGH Voltage Level
L = LOW Voltage Level
Outputs
O
H
H
H
L
DS009477-2
DSXXX
www.national.com
2
PrintDate=1997/08/28 PrintTime=12:25:31 10193 ds009477 Rev. No. 1 cmserv Proof
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