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PDF 74ACT374 Data sheet ( Hoja de datos )
| Número de pieza | 74ACT374 | |
| Descripción | OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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74ACT374
OCTAL D-TYPE FLIP FLOP
WITH 3 STATE OUTPUT NON INVERTING
s HIGH SPEED:
fMAX = 260 MHz (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 8 µA (MAX.) at TA = 25 oC
s COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN), VIL = 0.8V (MAX)
s 50Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 374
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The ACT374 is an advanced high-speed CMOS
OCTAL D-TYPE FLIP FLOP with 3 STATE
OUTPUT NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology. It is ideal for low
power applications mantaining high speed
operation similar to equivalent Bipolar Schottky
TTL.
These 8 bit D-Type flip-flops are controlled by a
clock input (CK) and an output enable input (OE).
PIN CONNECTION AND IEC LOGIC SYMBOLS
BM
(Plastic Package)
(Micro Package)
ORDER CODES :
74ACT374B
74ACT374M
On the positive transition of the clock, the Q
outputs will be set to logic state that were setup
at the D inputs.
While the (OE) input is low, the 8 outputs will be
in a normal logic state (high or low logic level)
and while high level the outputs will be in a high
impedance state.
The output control does not affect the internal
operation of flip flop; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
The device is designed to interface directly High
Speed CMOS system with TTL and NMOS
components.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
April 1997
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1 page  
74ACT374
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf =3 ns)
Symbol
P ar ame te r
tPLH Propagation Delay Time
tPHL CK to Q
tPZL Output Enable Time
tPZH
tPLZ Output Disable Time
tPHZ
tw CK Pulse Width, HIGH
or LOW
ts Setup Time Q to CK
HIGH or LOW
th Hold Time Q to CK
HIGH or LOW
fMAX Maximim Clock
Frequency
(*) Voltage range is 5V ± 0.5V
Test Condition
V CC
(V)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
Value
TA = 25 oC
-40 to 85 oC
Min. Typ. Max. Min. Max.
5.0 10.0
11.0
Unit
ns
6.0 10.0
11.0 ns
6.5 10.0
11.0 ns
1.5 5.0
5.0 ns
0.5 5.0
5.0 ns
-0.5 2.0
2.0 ns
100 260 85 MHz
CAPACITIVE CHARACTERISTICS
Symbol
P ar ame te r
Test Conditions
V CC
(V)
Value
TA = 25 oC
-40 to 85 oC
Min. Typ. Max. Min. Max.
Unit
COUT Output Capacitance
5.0
8 pF
CIN Input Capacitance
5.0
4 pF
CPD Power Dissipation
Capacitance (note 1)
5.0
25 pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to
Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/n (per circuit)
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74ACT374.PDF ] | |
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