|
|
PDF 74ACT2708PC Data sheet ( Hoja de datos )
| Número de pieza | 74ACT2708PC | |
| Descripción | 64 x 9 First-In/ First-Out Memory | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 74ACT2708PC (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
|
No Preview Available !
February 1989
Revised January 1999
74ACT2708
64 x 9 First-In, First-Out Memory
General Description
The ACT2708 is an expandable first-in, first-out memory
organized as 64 words by 9 bits. An 85 MHz shift-in and 60
MHz shift-out typical data rate makes it ideal for high-speed
applications. It uses a dual port RAM architecture with
pointer logic to achieve the high speed with negligible fall-
through time.
Separate Shift-In (SI) and Shift-Out (SO) clocks control the
use of synchronous or asynchronous write or read. Other
controls include a Master Reset (MR) and Output Enable
(OE) for initializing the internal registers and allowing the
data outputs to be 3-STATE. Input Ready (IR) and Output
Ready (OR) signal when the FIFO is ready for I/O opera-
tions. The status flags HF and FULL indicate when the
FIFO is full, empty or half full.
The FIFO can be expanded to provide different word
lengths by tying off unused data inputs.
Features
s 64-words by 9-bit dual port RAM organization
s 85 MHz shift-in, 60 MHz shift-out data rate, typical
s Expandable in word width only
s TTL-compatible inputs
s Asynchronous or synchronous operation
s Asynchronous master reset
s Outputs source/sink 8 mA
s 3-STATE outputs
s Full ESD protection
s Input and output pins directly in line for easy board lay-
out
s TRW 1030 work-alike operation
Applications
• High-speed disk or tape controllers
• A/D output buffers
• High-speed graphics pixel buffer
• Video time base correction
• Digital filtering
Ordering Code:
Order Number Package Number
Package Description
74ACT2708PC
N28B
28-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Assignment for DIP
Pin Names
D0–D8
MR
OE
SI
SO
IR
OR
HF
FULL
O0–O8
Description
Data Inputs
Master Reset
Output Enable Input
Shift-In
Shift-Out
Input Ready
Output Ready
Half Full Flag
Full Flag
Data Outputs
FACT™ is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010144.prf
www.fairchildsemi.com
1 page  
Mode 2: Master Reset
Sequence of Operation
1. Input and Output Ready, HF and FULL can be in any
state before the reset sequence with Master Reset
(MR) HIGH.
2. Master Reset goes LOW and clears the FIFO, setting
up all essential internal states. Master Reset must be
LOW pulse width tMRW before rising again.
3. Master Reset rises.
4. IR rises (if not HIGH already) to indicate ready to write
state recovery time tMRIRH after the falling edge of MR.
Both HF and FULL will go LOW indicating an empty
FIFO, occurring recovery times tMRE and tMRO respec-
tively after the falling edge of MR. OR falls recovery
time tMRORL after MR falls. Data at outputs goes LOW
recovery time tMRONL after MR goes LOW.
5. Shift-In can be taken HIGH after a minimum recovery
time tMRSIH after MR goes HIGH.
FIGURE 2. Mode of Operation Mode 2
5 www.fairchildsemi.com
5 Page 
AC Electrical Characteristics
Symbol
Parameter
tPLH
tPHL
tPLH
tPHL
tPLH
tPLH
tPLH
tPHL
tPHL
tPHL
tPHL
tPLH
tPHL
tPHL
tPLH
tPLH, tPHL
tPHL
tPLH
tPHL
tPLH
tPLH
tW
Propagation Delay, tIR
SI to IR
Propagation Delay, tIR
SI to IR
Propagation Delay, tIHF
SI to > HF
Propagation Delay, tIF
SI to Full Condition
Propagation Delay, tIE
SI to Not Empty
Propagation Delay, tIOR
SI to OR
Propagation Delay tMRIRH
MR to IR
Propagation Delay, tMRORL
MR to OR
Propagation Delay, tMRO
MR to Full Flag
Propagation Delay, tMRE
MR to HF Flag
Propagation Delay, tMRONL
MR to On, LOW
Propagation Delay, tD
SO to Data Out
Propagation Delay, tD
SO to Data Out
Propagation Delay, tOHF
SO to < HF
Propagation Delay, tOF
SO to Not Full
Propagation Delay, tOR
SO to OR
Propagation Delay, tOE
SO to Empty
Propagation Delay, tOD5
SI to New Data Out
Propagation Delay, tOD5
SI to New Data Out
Propagation Delay, tX1
SI to HF
Fall-Through Time, tFTO
SI to OR
R Pulse Width, tOP
VCC
(V)
(Note 5)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
TA = +25°C
CL = 50 pF
Min Typ Max
2.0 6.5 11.0
2.0 6.5 11.0
4.0
10.5
17.0
4.5
10.5
16.5
4.0
10.0
15.5
4.0
13.5
16.5
3.0 8.5 13.5
7.0
16.5
25.5
3.5 9.0 14.0
8.0
17.5
27.5
3.0 9.0 15.0
6.5
18.5
27.0
6.5
18.5
29.5
3.5 8.5 13.5
5.0
12.5
19.5
2.5 7.0 11.5
3.5 9.5 15.5
7.0
19.0
30.5
7.0
19.0
29.5
3.5
10.0
16.0
3.5
13.5
21.0
12.5
17.0
26.0
11
TA = −40°C to +85°C
CL = 50 pF
Min Max
1.5 12.5
Units
ns
1.5 12.0
ns
4.0 19.5
ns
4.5 19.5
ns
4.0 17.5
ns
4.0 19.0
ns
3.0 15.5
ns
7.0 29.0
ns
3.5 16.0
ns
8.0 30.5
ns
3.0 17.0
ns
6.5 31.0
ns
6.5 34.5
ns
3.5 15.5
ns
5.0 22.0
ns
2.5 13.5
ns
3.0 17.5
ns
6.0 35.5
ns
6.0 34.5
ns
2.5 18.0
ns
1.5 24.0
ns
12.5
30.5
ns
www.fairchildsemi.com
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet 74ACT2708PC.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 74ACT2708PC | 64 x 9 First-In/ First-Out Memory | Fairchild Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |