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PDF FDC6304P Data sheet ( Hoja de datos )
| Número de pieza | FDC6304P | |
| Descripción | Digital FET/ Dual P-Channel | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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July 1997
FDC6304P
Digital FET, Dual P-Channel
General Description
These P-Channel enhancement mode field effect transistor are
produced using Fairchild's proprietary, high cell density, DMOS
technology. This very high density process is tailored to minimize
on-state resistance at low gate drive conditions. This device is
designed especially for application in battery power applications
such as notebook computers and cellular phones. This device
has excellent on-state resistance even at gate drive voltages as
low as 2.5 volts.
Features
-25 V, -0.46 A continuous, -1.0 A Peak.
RDS(ON) = 1.5 Ω @ VGS= -2.7 V
RDS(ON) = 1.1 Ω @ VGS = -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. VGS(th) < 1.5 V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model.
SOT-23
SuperSOTTM-6
Mark: .304
SuperSOTTM-8
SO-8
SOT-223
SOIC-16
Absolute Maximum Ratings TA = 25oC unless other wise noted
Symbol Parameter
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage
ID Drain Current
- Continuous
- Pulsed
PD Maximum Power Dissipation
(Note 1a)
(Note 1b)
TJ,TSTG
ESD
Operating and Storage Temperature Range
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a)
RθJC
Thermal Resistance, Junction-to-Case
(Note 1)
© 1997 Fairchild Semiconductor Corporation
43
52
61
FDC6304P
-25
-8
-0.46
-1
0.9
0.7
-55 to 150
6.0
140
60
Units
V
V
A
W
°C
kV
°C/W
°C/W
FDC6304P Rev.D
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet FDC6304P.PDF ] | |
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