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Fairchild Semiconductor |
October 2003
Revised October 2004
FIN1217 • FIN1218 •
FIN1215 • FIN1216
LVDS 21-Bit Serializers/De-Serializers
General Description
The FIN1217 and FIN1215 transform 21-bit wide parallel
LVTTL (Low Voltage TTL) data into 3 serial LVDS (Low
Voltage Differential Signaling) data streams. A phase-
locked transmit clock is transmitted in parallel with the data
stream over a separate LVDS link. Every cycle of transmit
clock 21 bits of input LVTTL data are sampled and trans-
mitted.
The FIN1218 and FIN1216 receive and convert the 3 serial
LVDS data streams back into 21 bits of LVTTL data. Refer
to Table 1 for a matrix summary of the Serializers and De-
serializers available. For the FIN1217, at a transmit clock
frequency of 85 MHz, 21 bits of LVTTL data are transmitted
at a rate of 595 Mbps per LVDS channel.
These chipsets are an ideal solution to solve EMI and
cable size problems associated with wide and high-speed
TTL interfaces.
Features
s Low power consumption
s 20 MHz to 85 MHz shift clock support
s 50% duty cycle on the clock output of receiver
s ±1V common-mode range around 1.2V
s Narrow bus reduces cable size and cost
s High throughput (up to 1.785 Gbps throughput)
s Up to 595 Mbps per channel
s Internal PLL with no external component
s Compatible with TIA/EIA-644 specification
s Devices are offered in 48-lead TSSOP packages
Ordering Code:
Order Number Package Number
Package Description
FIN1215MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
FIN1216MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
FIN1217MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
FIN1218MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
© 2004 Fairchild Semiconductor Corporation DS500876
www.fairchildsemi.com
Part
FIN1217
FIN1218
FIN1215
FIN1216
TABLE 1. Serializers/De-Serializers Chip Matrix
CLK Frequency
85
85
66
66
LVTTL IN
21
21
LVDS OUT
3
3
LVDS IN LVTTL OUT
3 21
3 21
Package
48 TSSOP
48 TSSOP
48 TSSOP
48 TSSOP
Block Diagrams
Transmitter Functional Diagram for FIN1217 and FIN1215
Receiver Functional Diagram for FIN1218 and FIN1216
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