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LU6612 FASTCAT TM Single-FET for 10Base-T/100Base-TX



Agere Systems 로고
Agere Systems
LU6612 데이터시트, 핀배열, 회로
Data Sheet
July 2000
LU6612 FASTCAT TM Single-FET
for 10Base-T/100Base-TX
Features
General
10 Mbits/s Transceiver
s Compatible with IEEE * 802.3u 10Base-T standard
for twisted-pair cable
s Autopolarity detection and correction
s Adjustable squelch level for extended wire line
length capability (2 levels)
s Interfaces with IEEE 802.3u media independent
interface (MII)
s On-chip filtering eliminates the need for external fil-
ters
s Half- and full-duplex operations
100 Mbits/s Transceiver
s Compatible with IEEE 802.3u MII (clause 22), PCS
(clause 23), PMA (clause 24), autonegotiation
(clause 28), and PMD (clause 25) specifications
s Scrambler/descrambler bypass
s Encoder/decoder bypass
s 3-statable MII in 100 Mbits/s mode
s Selectable carrier sense signal generation (CRS
asserted during either transmission or reception in
half duplex, CRS asserted during reception only in
full duplex)
s Selectable MII or 5-bit code group interface
s Half- or full-duplex operations
s On-chip filtering and adaptive equalization that
eliminates the need for external filters
s Autonegotiation (IEEE 802.3u clause 28):
— Fast link pulse (FLP) burst generator
— Arbitration function
— Accepts preamble suppression
— Operates up to 12.5 MHz
s Supports the station management protocol and
frame format (clause 22):
— Basic and extended registers
— Supports next-page function
— Accepts preamble suppression
— Operates up to 12.5 MHz
s Supports the following management functions via
pins if station management is unavailable:
— Speed select
— Encoder/decoder bypass
— Scrambler/descrambler bypass
— Full duplex
— Autonegotiation
s Supports half- and full-duplex operations
s Provides four status signals: receive/transmit activ-
ity, full duplex, link integrity, and speed indication
s Powerdown mode for 10 Mbits/s and 100 Mbits/s
operation
s Loopback for 10 Mbits/s and 100 Mbits/s operation
s 0.35 µm low-power CMOS technology
s 64-pin TQFP
s Single 5 V power supply
* IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
Note: Advisories are issued as needed to update product information. When using this data sheet for design purposes, please contact
your Lucent Technologies Microelectronics Group Account Manager to obtain the latest advisory on this product.


LU6612 데이터시트, 핀배열, 회로
LU6612
FASTCAT Single-FET for 10Base-T/100Base-TX
Data Sheet
July 2000
Contents
Table of Contents
Page
Features .................................................................................................................................................................... 1
10 Mbits/s Transceiver ............................................................................................................................................ 1
100 Mbits/s Transceiver .......................................................................................................................................... 1
General ................................................................................................................................................................... 1
Description................................................................................................................................................................. 4
Pin Information and Descriptions............................................................................................................................... 8
MII Station Management .........................................................................................................................................13
Basic Operations...................................................................................................................................................13
MII Management Frames ......................................................................................................................................13
MODE Selection ......................................................................................................................................................23
Absolute Maximum Ratings (TA = 25 °C) ................................................................................................................24
Electrical Characteristics .........................................................................................................................................24
Timing Characteristics (Preliminary)........................................................................................................................25
Outline Diagram.......................................................................................................................................................34
64-Pin TQFP .........................................................................................................................................................34
Technical Document Types .....................................................................................................................................35
Ordering Information................................................................................................................................................36
List of Tables
Tables
Page
Table 1. MII/Serial Interface Pins (17) ..................................................................................................................... 9
Table 2. MII Management Pins (2) ........................................................................................................................ 10
Table 3. 10/100 Mbits/s Twisted-Pair (TP) Interface Pins (4) ................................................................................ 10
Table 4. Ground and Power Pins (21) ................................................................................................................... 11
Table 5. Miscellaneous Pins (20) .......................................................................................................................... 11
Table 5 . Miscellaneous Pins (20) (continued) ....................................................................................................... 12
Table 6. MII Management Frame Fields and Format ............................................................................................. 13
Table 7. MII Management Frame Descriptions ...................................................................................................... 13
Table 8. MII Management Registers (MR) ............................................................................................................. 14
Table 9. MR0—Control Register Bit Descriptions .................................................................................................. 15
Table 10. MR1—Status Register Bit Descriptions ................................................................................................. 16
Table 11. MR2, 3—PHY Identifier Registers (1 and 2) Bit Descriptions ................................................................ 17
Table 12. MR4—Autonegotiation Advertisement Register Bit Descriptions........................................................... 17
Table 13. MR5—Autonegotiation Link Partner (LP) Ability Register Bit Descriptions (Base_Page) ...................... 18
Table 14. MR5—Autonegotiation Link Partner (LP) Ability Register Bit Descriptions (Next_Page) ....................... 18
Table 15. MR6—Autonegotiation Expansion Register Bit Descriptions................................................................. 19
Table 16. MR7—Next_Page Transmit Register Bit Descriptions............................................................................ 19
Table 17. MR28—Device-Specific Register 1 (Status Register) Bit Descriptions ................................................. 20
Table 18. MR29—Device-Specific Register 2 (100 Mbits/s Control) Bit Descriptions ........................................... 21
Table 19. MR30—Device-Specific Register 3 (10 Mbits/s Control) Bit Descriptions ............................................. 22
Table 20. Operation Modes of LU6612 ................................................................................................................. 23
Table 21. LU6612 Crystal Specifications ............................................................................................................... 23
Table 22 . Absolute Maximum Ratings .................................................................................................................. 24
Table 23 . Operating Conditions ............................................................................................................................ 24
Table 24. dc Characteristics................................................................................................................................... 24
Table 25. MII Management Interface Timing (25 pF Load) .................................................................................... 25
Table 26. MII Data Timing (25 pF Load) ................................................................................................................ 26
Table 27. Serial 10 Mbits/s Timing for RX/RY, CRS, and RX_CLK ........................................................................ 28
2 Lucent Technologies Inc.




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