ADF4208 반도체 회로 부품 판매점
Dual RF PLL Frequency Synthesizers
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 Analog Devices |
Dual RF PLL Frequency Synthesizers
ADF4206/ADF4208
FEATURES
ADF4206: 550 MHz/550 MHz
ADF4208: 2.0 GHz/1.1 GHz
2.7 V to 5.5 V power supply
Selectable charge pump supply (VP) allows extended
tuning voltage in 3 V systems
Selectable charge pump currents
On-chip oscillator circuit
Selectable dual modulus prescaler
RF2: 32/33 or 64/65
RF1: 32/33 or 64/65
3-wire serial interface
Power-down mode
APPLICATIONS
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Base stations for wireless radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless LANS
Communications test equipment
CATV equipment
GENERAL DESCRIPTION
The ADF420x family of dual frequency synthesizers are used
to implement local oscillators in the upconversion and down-
conversion sections of wireless receivers and transmitters. Each
synthesizer consists of a low noise, digital, phase frequency detector
(PFD); a precision charge pump; a programmable reference
divider; programmable A and B counters; and a dual modulus
prescaler (P/P + 1). The A (6-bit) and B (11-bit) counters, in
conjunction with the dual modulus prescaler (P/P + 1), implement
an N divider (N = BP + A). In addition, the 14-bit reference
counter (R counter) allows selectable REFIN frequencies at the
PFD input. The on-chip oscillator circuitry allows the reference
input to be derived from crystal oscillators.
A complete phase-locked loop (PLL) can be implemented if the
synthesizers are used with an external loop filter and voltage
controlled oscillators (VCOs).
Control of all the on-chip registers is via a simple 3-wire
interface. The devices operate with a power supply ranging
from 2.7 V to 5.5 V and can be powered down when not in use.
RF2INA
RF2INB
OSCIN
OSCOUT
CLK
DATA
LE
RF1INA
RF1INB
FUNCTIONAL BLOCK DIAGRAM
VDD1
VDD2
VP1
VP2
N = BP + A
RF2
PRESCALER
OSCILLATOR
22-BIT
DATA
REGISTER
SDOUT
N = BP + A
RF1
PRESCALER
11-BIT RF2
B-COUNTER
6-BIT RF2
A-COUNTER
14-BIT RF2
R-COUNTER
14-BIT RF1
R-COUNTER
11-BIT RF1
B-COUNTER
6-BIT RF1
A-COUNTER
ADF4206/ADF4208
PHASE
COMPARATOR
RF2
LOCK
DETECT
CHARGE
PUMP
CPRF2
OUTPUT
MUX
MUXOUT
RF1
LOCK
DETECT
PHASE
COMPARATOR
CHARGE
PUMP
CPRF1
DGNDRF1
AGNDRF1 DGNDRF2
Figure 1.
AGNDRF2
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
ADF4206/ADF4208
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
Timing Diagram ........................................................................... 5
Absolute Maximum Ratings............................................................ 6
Transistor Count........................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Circuit Description......................................................................... 11
Reference Input Section............................................................. 11
RF Input Stage............................................................................. 11
Prescaler....................................................................................... 11
A and B Counters ....................................................................... 11
REVISION HISTORY
2/06—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Deleted ADF4207 ...............................................................Universal
Changes to Table 3............................................................................ 6
Changes to Function Description .................................................. 7
Changes to Table 4............................................................................ 7
Changes to Figure 22 Caption....................................................... 12
Changes to Pulse Swallow Function ............................................ 13
Changes to Figure 29...................................................................... 15
Changes to Figure 31...................................................................... 17
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 25
3/01—Revision 0: Initial Version
Pulse Swallow Function............................................................. 11
R Counter .................................................................................... 11
Phase Frequency Detector (PFD) and Charge Pump............ 12
MUXOUT and Lock Detect...................................................... 12
Lock Detect ................................................................................. 12
Input Shift Register .................................................................... 12
Program Modes .............................................................................. 18
Power-Down ............................................................................... 18
IF Section (RF2) ......................................................................... 18
RF Section (RF1) ........................................................................ 19
Applications Section....................................................................... 20
Local Oscillator for GSM Handset Receiver........................... 20
Local Oscillator for WCDMA Receiver .................................. 21
Interfacing ....................................................................................... 22
ADuC812 Interface .................................................................... 22
ADSP-2181 Interface ................................................................. 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 24
Rev. A | Page 2 of 24
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관련 데이터시트
ADF4206
Dual RF PLL Frequency Synthesizers - Analog Devices
ADF4207
Dual RF PLL Frequency Synthesizers - Analog Devices
ADF4208
Dual RF PLL Frequency Synthesizers - Analog Devices