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PDF AB28F200BR-T80 Data sheet ( Hoja de datos )
| Número de pieza | AB28F200BR-T80 | |
| Descripción | 2-MBIT (128K X 16/ 256K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY | |
| Fabricantes | Intel Corporation | |
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E
ADVANCE INFORMATION
A28F200BR-T/B
2-MBIT (128K X 16, 256K X 8)
SmartVoltage BOOT BLOCK
FLASH MEMORY FAMILY
Automotive
n Intel SmartVoltage Technology
5V or 12V Program/Erase
5V Read Operation
n Very High Performance Read
80 ns Max. Access Time,
40 ns Max. Output Enable Time
n Low Power Consumption
Maximum 65 mA Read Current at 5V
n x8/x16-Selectable Input/Output Bus
High Performance 16- or 32-bit
CPUs
n Optimized Array Blocking Architecture
One 16-KB Protected Boot Block
Two 8-KB Parameter Blocks
One 96-KB Main Block
One 128-KB Main Block
Top or Bottom Boot Locations
n Hardware-Protection for Boot Block
n Software EEPROM Emulation with
Parameter Blocks
n Automotive Temperature Operation
-40°C to +125°C
n Extended Cycling Capability
30,000 Block Erase Cycles for
Parameter Blocks
1,000 Block Erase Cycles for Main
Blocks
n Automated Word/Byte Program and
Block Erase
Industry-Standard Command User
Interface
Status Registers
Erase Suspend Capability
n SRAM-Compatible Write Interface
n Automatic Power Savings Feature
1 mA Typical ICC Active Current in
Static Operation
n Reset/Deep Power-Down Input
0.2 µA ICCTypical
Provides Reset for Boot Operations
n Hardware Data Protection Feature
Program/Erase Lockout during
Power Transitions
n Industry-Standard Surface Mount
Packaging
44-Lead PSOP: JEDEC ROM
Compatible
n ETOX™ IV Flash Technology
April 1997
Order Number: 290542-003
1 page  
E
1.0 PRODUCT FAMILY OVERVIEW
This datasheet contains the specifications for the
automotive version of the 28F200BR family of boot
block flash memory devices.
This device continues to offer the same
functionality as earlier “BX” devices but adds the
capability of performing program and erase
operations with a 5V or 12V VPP. The A28F200BR
automatically senses which voltage is applied to
the VPP pin and adjusts its operation accordingly.
1.1 New Features in the
SmartVoltage Products
The new SmartVoltage boot block flash memory
family offers identical operation as the current
BX/BL 12V program products, except for the
differences listed below. All other functions are
equivalent to current products, including
signatures, write commands, and pinouts.
• WP# pin has replaced a DU pin. See Table 1
for details.
• 5V program/erase operation has been added
that uses proven program and erase
techniques with 5V ± 10% applied to VPP.
If you are designing with existing BX 12V VPP boot
block products today, you should provide the
capability in your board design to upgrade to these
new SmartVoltage products.
Follow these guidelines to ensure compatibilty:
1. Connect WP# (DU on existing products) to a
control signal, VCC or GND.
2. If adding a switch on VPP for write protection,
switch to GND for complete write protection.
3. Allow for connecting 5V to VPP instead of 12V,
if desired.
1.2 Main Features
Intel’s SmartVoltage technology provides the most
flexible voltage solution in the industry.
SmartVoltage provides two discrete voltage supply
pins, VCC for read operation, and VPP for program
and erase operation. Discrete supply pins allow
system designers to use the optimal voltage levels
for their design. For program and erase
ADVANCE INFORMATION
A28F200BR
operations, 5V VPP operation eliminates the need
for in system voltage converters, while 12V VPP
operation provides faster program and erase for
situations where 12V is available, such as
manufacturing or designs where 12V is already
available.
The 28F200 boot block flash memory family is a
very high-performance, 2-Mbit (2,097,152 bit) flash
memory family organized as either 256 Kwords
(131,072 words) of 16 bits each or 512 Kbytes
(262,144 bytes) of 8 bits each.
Separately erasable blocks, including a hardware-
lockable boot block (16,384 bytes), two parameter
blocks (8,192 Bytes each) and main blocks (one
block of 98,304 bytes and one block of 131,072
bytes) define the boot block flash family
architecture. See Figure 3 for memory maps. Each
parameter block can be independently erased and
programmed 10,000 times. Each main block can
be erased 1,000 times.
The boot block is located at either the top
(denoted by -T suffix) or the bottom (-B suffix) of
the address map in order to accommodate
different microprocessor protocols for boot code
location. The hardware-lockable boot block
provides complete code security for the kernel
code required for system initialization. Locking and
unlocking of the boot block is controlled by WP#
and/or RP# (see Section 3.4 for details).
The Command User Interface (CUI) serves as the
interface between the microprocessor or
microcontroller and the internal operation of the
boot block flash memory products. The internal
Write State Machine (WSM) automatically
executes the algorithms and timings necessary for
program and erase operations, including
verifications, thereby unburdening the
microprocessor or microcontroller of these tasks.
The Status Register (SR) indicates the status of
the WSM and whether it successfully completed
the desired program or erase operation.
Program and erase automation allows program
and erase operations to be executed using an
industry-standard two-write command sequence to
the CUI. Data writes are performed in word or byte
increments. Each byte or word in the flash
memory can be programmed independently of
other memory locations, unlike erases, which
erase all locations within a block simultaneously.
The 4-Mbit SmartVoltage boot block flash memory
family is also designed with an Automatic Power
5
5 Page 
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A28F200BR
Table 2. Bus Operations for Word-Wide Mode (BYTE# = VIH)
Mode
Notes RP# CE# OE# WE# A9
A0 VPP
Read
1,2,3 VIH VIL VIL VIH
X
X
X
Output Disable
VIH VIL VIH VIH
X
X
X
Standby
VIH VIH
X
X
X
XX
Deep Power-Down
9 VIL X X X X X X
Intelligent Identifier (Mfr) 4
VIH VIL VIL VIH VID VIL
X
Intelligent Identifier
(Device)
4,5 VIH VIL VIL VIH VID VIH
X
Write
6,7,8 VIH
VIL VIH
VIL
X
X
X
DQ0-15
DOUT
High Z
High Z
High Z
0089 H
See Table 4
DIN
Mode
Read
Output Disable
Standby
Deep Power-
Down
Table 3. Bus Operations for Byte-Wide Mode (BYTE# = VIL)
Notes RP# CE# OE# WE# A9
A0 A-1 VPP
1,2,3 VIH VIL VIL VIH
X
X
XX
VIH VIL VIH VIH
X
X
XX
VIH VIH
X
X
X
X
XX
9 VIL X X X X X X X
DQ0-7
DOUT
High Z
High Z
High Z
DQ8-14
High Z
High Z
High Z
High Z
Intelligent
Identifier (Mfr)
4
VIH VIL VIL VIH VID VIL X X
89H High Z
Intelligent
Identifier
(Device)
4,5 VIH VIL VIL VIH VID VIH X X
See High Z
Table 4
Write
6,7,8 VIH VIL VIH VIL
X
X
XX
DIN
NOTES:
1. Refer to DC Characteristics.
2. X can be VIL, VIH for control pins and addresses, VPPLK or VPPH for VPP.
3. See DC Characteristics for VPPLK, VPPH1, VPPH2, VHH, VID voltages.
4. Manufacturer and Device codes may also be accessed via a CUI write sequence, A1-A17 = X, A1-A18 = X.
5. See Table 4 of Device IDs.
6. Refer to Table 5 for valid DIN during a write operation.
7. Command writes for Block Erase or Word/ByteProgram are only executed when VPP = VPPH1 or VPPH2.
8. To program or erase the boot block, hold RP# at VHH or WP# at VIH.
9. RP# must be at GND ± 0.2V to meet the maximum deep power-down current specified.
High Z
ADVANCE INFORMATION
11
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