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AD28MSP01 반도체 회로 부품 판매점

PSTN Signal Port



Analog Devices 로고
Analog Devices
AD28MSP01 데이터시트, 핀배열, 회로
a
PSTN Signal Port
AD28msp01
FEATURES
Complete Analog l/O Port for DSP-Based FAX/MODEM
Applications
Linear-Coded 16-Bit Sigma-Delta ADC
Linear-Coded 16-Bit Sigma-Delta DAC
On-Chip Anti-Alias and Anti-lmage Filters
Digital Resampling/lnterpolation Filter
7.2 kHz, 8.0 kHz, and 9.6 kHz Sampling Rates
8/7 Mode for 8.23 kHz, 9.14 kHz, and 10.97 kHz
Sampling Rates
Synchronous and Asynchronous DAC/ADC Modes
Bit and Baud Clock Generation
Transmit Digital Phase-Locked Loop for Terminal
Synchronization
Independent Transmit and Receive Phase Adjustment
Serial Interface to DSP Processors
+5 V Operation with Power-Down Mode
28-Pin Plastic DlP/44-Lead PLCC/28-Lead SOIC
APPLICATIONS
High Performance DSP-Based Modems
V.32ter, V.32bis, V.32, V.22bis, V.22, V.21,
Bell 212A, 103
Fax and Cellular-Compatible Modems
V.33, V.29, V.27ter, V.27bis, V.27, V.26bis
Integrated Fax, Modem, and Speech Processing
FUNCTIONAL BLOCK DIAGRAM
ANALOG
INPUTS
16-BIT
SIGMA-DELTA
ADC
VOLTAGE
REFERENCE
RESAMPLING
INTERPOLATION
FILTER
SERIAL
PORT
DIGITAL
DATA AND
CONTROL
DIFFERENTIAL
ANALOG
OUTPUT
16-BIT
SIGMA-DELTA
DAC
CLOCK INPUTS
CLOCK OUTPUTS
CLOCK
GENERATION
GENERAL DESCRIPTION
The AD28msp01 is a complete analog front end for high perfor-
mance DSP-based modems. The device includes all data conver-
sion, filtering, and clock generation circuitry needed to imple-
ment an echo-cancelling modem with a single host digital signal
processor. Software-programmable sample rates and clocking
modes support all established modem standards. The AD28msp01
simplifies overall system design by requiring only +5 volts.
The inclusion of on-chip anti-aliasing and anti-imaging filters
and 16-bit sigma-delta ADC and DAC ensures a highly inte-
grated and compact solution for FAX or data MODEM applica-
tions. Sigma-delta conversion technology eliminates the need for
complex off-chip anti-aliasing filters and sample-and-hold circuitry.
The AD28msp01 utilizes advanced sigma-delta technology to
move the entire echo-cancelling modem implementation into the
digital domain. The device maintains a –72 dB SNR throughout
all filtering and data conversion. Purely DSP-based echo cancel-
lation algorithms can thereby maintain robust bit error rates
under worst-case signal attenuation and echo amplitude condi-
tions. The AD28msp01’s on-chip interpolation filter resamples
the received signal after echo cancellation in the DSP, freeing
the processor for other voice or data communications tasks.
On-chip bit and baud clock generation circuitry provides for
either synchronous or asynchronous operation of the transmit
(DAC) and receive (ADC) paths. Each path features indepen-
dent phase advance and retard adjustments via software control.
The AD28msp01 can also synchronize modem operation to an
external terminal bit clock.
The AD28msp01’s serial I/O port provides an easy interface to
host DSP microprocessors such as the ADSP-2101, ADSP-2105,
and ADSP-2111. Packaged in a 28-pin plastic DIP, 44-lead
PLCC, 44-pin TQFP, or 28-lead SOIC, the AD28msp01 pro-
vides a compact solution for space-constrained environments.
The device operates from a +5 V supply and offers a low power
sleep mode for battery-powered systems.
A detailed block diagram of the AD28msp01 is shown in
Figure 1.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703


AD28MSP01 데이터시트, 핀배열, 회로
AD28msp01
VFB
VIN
VOUT+
VOUT–
16-BIT SIGMA-DELTA ADC
INPUT
AMP
ANALOG
1
SIGMA-DELTA
MODULATOR
DIGITAL 16
DECIMATION
FILTER
DIGITAL
16
ANTI-ALIASING
LOW-PASS FILTER
DIGITAL
HIGH-PASS
FILTER
16
1.728 MHz
28.8/32.0/38.4 kHz
7.2/8.0/9.6 kHz
7.2/8.0/9.6 kHz
SDOFS
SDO
500k
VOLTAGE
REFERENCE
RESAMPLING
INTERPOLATION
FILTER
OUTPUT
DIFF.
AMP
TSYNC
ANALOG
SMOOTHING
FILTER
16-BIT SIGMA-DELTA DAC
1 DIGITAL
SIGMA-DELTA
MODULATOR
16
DIGITAL
INTERPOLATION
FILTER
16
DIGITAL
ANTI-IMAGING
LOW-PASS
FILTER
16
1.728 MHz
1.728 MHz
28.8/32.0/38.4 kHz
7.2/8.0/9.6 kHz
INTERNAL CLOCK
CLOCK GENERATION
CONTROL CIRCUITRY
AND
SEQUENCER
CONTROL
REGISTERS
SERIAL
PORT
SCLK
SDI
SDIFS
tCONV tBAUD tBIT
rCONV rBAUD rBIT
MCLK
RESET
CS
Figure 1. AD28msp01 Block Diagram
PIN DESCRIPTIONS
Name Type Description
Name Type Description
Analog Interface
VIN I Analog input to the inverting terminal of the
input amplifier.
VFB
VOUTP
O
O
Feedback terminal of the input amplifier.
Analog output from the noninverting terminal
of the output differential amplifier.
VOUTN O
Analog output from inverting terminal of the
output differential amplifier.
Serial Interface
SCLK O/Z Serial clock used for clocking data or control
bits to/from the serial port (SPORT). The
frequency of this clock is 1.7280 MHz. This
pin is 3-stated when the CS is low.
SDI I Serial data input of the SPORT. Both data
and control information are input on this pin.
This pin is ignored when CS is low.
SDO O/Z Serial data output of the SPORT. Both data
and control information are output on this
pin. This pin is 3-stated when CS is low.
SDIFS I Framing synchronization signal for serial data
transfers to the AD28msp01 (via the SDI
pin). This pin is ignored when CS is low.
SDOFS O/Z Framing synchronization signal for serial data
transfers from the AD28msp01 (via the SDO
pin). This pin is 3-stated when CS is low.
Clock Generation
TSYNC I Transmit synchronization clock. This signal is
used to synchronize the transmit clocks and
the converter clocks to an external terminal/
bit-rate clock. It is used in the V.32 TSYNC
and Asynchronous TSYNC modes and is
ignored in other operating modes. The
frequency of the external clock must be
programmed in Control Register 0. This pin
must be tied high or low if it is not being
used.
TBIT O Transmit bit rate clock. This is an output
clock whose frequency is programmable via
Control Register 3. It is synchronized with
the TCONV clock.
TBAUD O Transmit baud rate clock. This is an output
clock whose frequency is programmable via
Control Register 3. It is synchronized with
the TCONV clock.
–2– REV. A




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