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AD261 반도체 회로 부품 판매점

High Speed/ Logic Isolator



Analog Devices 로고
Analog Devices
AD261 데이터시트, 핀배열, 회로
a
High Speed, Logic Isolator
AD261
FEATURES
Isolation Test Voltage: To 3.5 kV rms
Five Isolated Logic Lines: Available in Six I/O Configurations
Logic Signal Bandwidth: 20 MHz (min)
CMV Transient Immunity: 10 kV/s min
Waveform Edge Transmission Symmetry: ؎1 ns
Field and System Output Enable/Three-State Functions
Performance Rated Over –25؇C to +85؇C
UL1950, IEC950, EN60950 Certification (VDE, CE, Pending)
APPLICATIONS
PLC/DCS Analog Input and Output Cards
Communications Bus Isolation
General Data Acquisition Applications
IGBT Motor Drive Controls
High Speed Digital I/O Ports
GENERAL DESCRIPTION
The AD261 is designed to isolate five digital control signals
to/from a microcontroller and its related field I/O components.
Six models allow all I/O combinations from five input lines to
five output lines, including combinations in between. Every
AD261 effectively replaces up to five opto-isolators.
Each line of the AD261 has a bandwidth of 20 MHz (min) with
a propagation delay of only 14 ns, which allows for extremely
fast data transmission. Output waveform symmetry is maintained
to within ± 1 ns of the input so the AD261 can be used to accu-
rately isolate time-based PWM signals.
All field or system output pins of the AD261 can be set to a high
resistance three-state level by use of the two enable pins. A field
output three-stated offers a convenient method of presetting
logic levels at power-up by use of pull-up/down resistors. Sys-
tem side outputs being three-stated allows for easy multiplexing
of multiple AD261s.
The isolation barrier of the AD261 B Grade is 100% tested
as high as 3.5 kV rms (system to field). The barrier design also
provides excellent common-mode transient immunity from
10 kV/µs common-mode voltage excursions of field side termi-
nals relative to the system side, with no false output triggering
on either side.
Each output is updated within nanoseconds by input logic tran-
sitions, the AD261 also has a continuous output update feature
that automatically updates each output based on the dc level of
the input. This guarantees the output is always valid 10 µs after
a fault condition or after the power-up reset interval.
FUNCTIONAL BLOCK DIAGRAM
LATCH
F0
STTHARTEEE-
LINE 0
D
E
S0
LATCH
F1
STTHARTEEE-
LINE 1
D
E
2 S1
LATCH
F2
STTHARTEEE-
LINE 2
D
E
3 S2
LATCH
F3
D
E
LINE 3
THSRTAETEE-
4 S3
LATCH
F4
D
E
LINE 4
THSRTAETEE-
5 S4
ENABLEFLD 17
+5V dcFLD 16 +5V dc
5Vdc RTN
5V RTNFLD 15
6 ENABLESYS
+5V dc
7 +5V dcSYS
5Vdc RTN
8 5V RTNSYS
FIELD
SYSTEM
TYPICAL MODEL
(AD261-2)
PRODUCT HIGHLIGHTS
Six Isolated Logic Line I/O Configurations Available: The
AD261 is available in six pin-compatible versions of I/O con-
figurations to meet a wide variety of requirements.
Wide Bandwidth with Minimal Edge Error: The AD261
affords extremely fast isolation of logic signals due to its 20 MHz
bandwidth and 14 ns propagation delay. It maintains a wave-
form input-to-output edge transition error of typically less than
± 1 ns (total) for positive vs. negative transition.
3.5 kV rms Test Voltage Isolation Rating: The AD261
B Grade is rated to operate at 1.25 kV rms and is 100% pro-
duction tested at 3.5 kV rms, using a standard ADI test method.
High Transient Immunity: The AD261 rejects common-
mode transients slewing at up to 10 kV/µs without false trigger-
ing or damage to the device.
(Continued on page 5)
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1997


AD261 데이터시트, 핀배열, 회로
AD261–SPECIFICATIONS (Typical at TA = +25؇C, +5 V dcSYS, +5 V dcFLD, tRR = 50 ns max unless otherwise noted)
Parameter
Conditions
Min Typ Max
Units
INPUT CHARACTERISTICS
Threshold Voltage
Positive Transition (VT+)
Negative Transition (VT–)
Hysteresis Voltage (VH)
Input Capacitance (CIN)
Input Bias Current (IIN)
+5 V dcSYS = 4.5 V
+5 V dcSYS = 5.5 V
+5 V dcSYS = 4.5 V
+5 V dcSYS = 5.5 V
+5 V dcSYS = 4.5 V
+5 V dcSYS = 5.5 V
Per Input
2.0 2.7
3.0 3.2
0.9 1.8
1.2 2.2
0.4 0.9
0.5 1.0
5
0.5
3.15
4.2
2.2
3.0
1.4
1.5
V
V
V
V
V
V
pF
µA
OUTPUT CHARACTERISTICS
Output Voltage1
High Level (VOH)
Low Level (VOL)
Output Three-State Leakage Current
+5 V dcSYS = 4.5 V, |IO| = 0.02 mA
+5 V dcSYS = 4.5 V, |IO| = 4 mA
+5 V dcSYS = 4.5 V, |IO| = 0.02 mA
+5 V dcSYS = 4.5 V, |IO| = 4 mA
ENABLESYS/FLD @ Logic Low/High Level Respectively
4.4
3.7
0.5
0.1
0.4
V
V
V
V
µA
DYNAMIC RESPONSE 1 (Refer to Figure 2)
Max Logic Signal Frequency (fMIN)
Waveform Edge Symmetry Error (tERROR)
Logic Edge Propagation Delay (tPHL, tPLH)
Minimum Pulsewidth (tPWMIN)
Max Output Update Delay on Fault or After
Power-Up Reset Interval (30 µs)2
50% Duty Cycle, +5 V dcSYS = 5 V
tPHL vs. tPLH
20
±1
14
25
12
25
MHz
ns
ns
ns
µs
ISOLATION BARRIER RATING3
Operating Isolation Voltage (VCMV)
Isolation Rating Test Voltage (VCMV TEST)4
Transient Immunity (VTRANSIENT)
Isolation Mode Capacitance (CISO)
Capacitive Leakage Current (ILEAD)
AD261A
AD261B
AD261A
AD261B
Total Capacitance, All Lines
240 V rms @ 60 Hz
1750
3500
10,000
9
375
1250
15
2
V rms
V rms
V rms
V rms
V/µs
pF
µA rms
POWER SUPPLY
Supply Voltage (+5 V dcSYS and +5 V dcFLD)
Power Dissipation Capacitance
Quiescent Supply Current
Supply Current
Rated Performance
Operating
Effective, per Input, Either Side
Effective per Output, Either Side—No Load
Each, +5 V dcSYS & FLD
All Lines @ 10 MHz (Sum of +5 V dcSYS & FLD)
4.5
4.0
8
28
4
18
5.5
5.75
V dc
V dc
pF
pF
mA
mA
TEMPERATURE RANGE
Rated Performance (TA)5
Storage (TSTG)
–25 +85 °C
–40 +85 °C
NOTES
1For best performance, bypass +5 V dc supplies to com., at or near the device (0.01 µF). +5 V dc supplies are also internally bypassed with 0.05 µF.
2As the supply voltage is applied to either side of the AD261, the internal circuitry will go into a power-up reset mode (all lines disabled) for about 30 µs after the point
where +5 V dcSYS & FLD passes above 3.3 V.
3“Operating” isolation voltage is derived from the Isolation Test Voltage in accordance with such methods as found in VDE-0883 wherein a device will be “hi-pot”
tested at twice the operating voltage, plus one thousand volts. Partial discharge testing, with an acceptance threshold of 80 pC of discharge may be considered the
same as a hi-pot test (but nondestructive).
4Partial Discharge at 80 pC THLD.
5Supply Current will increase slightly, but otherwise the unit will function within specification to –40°C.
Specifications are subject to change without notice.
–2– REV. 0




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