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PDF AD5233 Data sheet ( Hoja de datos )
| Número de pieza | AD5233 | |
| Descripción | Quad 64-Position Digital Potentiometer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD5233 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Nonvolatile Memory, Quad
64-Position Digital Potentiometer
AD5233
FEATURES
Nonvolatile memory stores wiper setting
4-channel independent programmable
64-position resolution
Power-on refreshed with EEMEM settings
EEMEM restore time: 140 μs typical
Full monotonic operation
10 kΩ, 50 kΩ, and 100 kΩ terminal resistance
Permanent memory write protection
Wiper setting readback
Predefined linear increment/decrement instructions
Predefined ±6 dB/step log taper increment/decrement
instructions
SPI-compatible serial interface with readback function
2.7 V to 5.5 V single supply or ±2.5 V dual supply
11 bytes extra nonvolatile memory for user-defined data
100-year typical data retention, TA = 55°C
APPLICATIONS
Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Programmable voltage-to-current conversion
Programmable filters, delays, time constants
Programmable power supply
Sensor calibration
GENERAL DESCRIPTION
The AD5233 is a quad-channel nonvolatile memory,1 digitally
controlled potentiometer2 with a 64-step resolution. The device
performs the same electronic adjustment function as a mechanical
potentiometer with enhanced resolution, solid-state reliability,
and remote controllability. The AD5233 has versatile program-
ming using a serial peripheral interface (SPI) for 16 modes of
operation and adjustment, including scratchpad programming,
memory storing and restoring, increment/decrement, ±6 dB/step
log taper adjustment, wiper setting readback, and extra EEMEM
for user-defined information such as memory data for other
components, look-up tables, or system identification
information.
1 The terms nonvolatile memory and EEMEM are used interchangeably.
2 The terms digital potentiometer and RDAC are used interchangeably.
FUNCTIONAL BLOCK DIAGRAM
CS
CLK
SDI
SDO
ADDR
DECODE
SDI SERIAL
INTERFACE
SDO
RDAC1
REGISTER
AD5233
EEMEM1
RDAC1
WP
RDY
EEMEM
CONTROL
RDAC2
REGISTER
11 BYTES
USER EEMEM
O1 DIGITAL
O2
OUTPUT
BUFFER
2
DIGITAL 5
REGISTER
PR
EEMEM2
RDAC3
REGISTER
EEMEM3
RDAC4
REGISTER
RDAC2
RDAC3
GND
EEMEM5
EEMEM4
RDAC4
Figure 1.
VDD
A1
W1
B1
A2
W2
B2
A3
W3
B3
A4
W4
B4
VSS
In the scratchpad programming mode, a specific setting can
be programmed directly to the RDAC register, which sets the
resistance between Terminal W to Terminal A and Terminal W
to Terminal B. This setting can be stored into the EEMEM and
is transferred automatically to the RDAC register during system
power-on.
The EEMEM content can be restored dynamically or through
external PR strobing. A WP function protects EEMEM contents.
To simplify the programming, independent or simultaneous
increment or decrement commands can be used to move the
RDAC wiper up or down, one step at a time. For logarithmic
±6 dB step changes in wiper settings, the left or right bit shift
command can be used to double or halve the RDAC wiper
setting.
The AD5233 is available in a thin 24-lead TSSOP package. The
part is guaranteed to operate over the extended industrial
temperature range of −40°C to +85°C.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2008 Analog Devices, Inc. All rights reserved.
1 page  
AD5233
TIMING CHARACTERISTICS
VDD = 3 V to 5.5 V, VSS = 0 V, and −40°C < TA < +85°C, unless otherwise noted.
Table 2.
Parameter
INTERFACE TIMING CHARACTERISTICS2, 3
Clock Cycle Time (tCYC)
CS Setup Time
CLK Shutdown Time to CS Rise
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CS to SDO-SPI Line Acquire
CS to SDO-SPI Line Release
CLK to SDO Propagation Delay4
CLK to SDO Data Hold Time
CS High Pulse Width5
CS High to CS High5
RDY Rise to CS Fall
CS Rise to RDY Fall Time
Read/Store to Nonvolatile EEMEM6
CS Rise to Clock Rise/Fall Setup
Preset Pulse Width (Asynchronous)
Preset Response Time to Wiper Setting
Power-On EEMEM Restore Time
FLASH/EE MEMORY RELIABILITY
Endurance7
Data Retention8
Symbol
t1
t2
t3
t4, t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
tPRW
tPRESP
tEEMEM1
Conditions
Clock level high or low
From positive CLK transition
From positive CLK transition
RPULL-UP = 2.2 kΩ, CL < 20 pF
RP = 2.2 kΩ, CL < 20 pF
Applies to Instruction 0x2, Instruction 0x3,
and Instruction 0x9
Not shown in timing diagram
PR pulsed low to refresh wiper positions
RAB = 10 kΩ
Min
20
10
1
10
5
5
0
10
4
0
10
50
100
Typ1 Max
40
50
50
0.1 0.15
25
70
140
100
Unit
ns
ns
tCYC
ns
ns
ns
ns
ns
ns
ns
ns
tCYC
ns
ms
ms
ns
ns
μs
μs
kCycles
Years
1 Typicals represent average readings at 25°C and VDD = 5 V.
2 Guaranteed by design and not subject to production test.
3 See the timing diagrams (Figure 2 and Figure 3) for the location of the measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V)
and timed from a voltage level of 1.5 V. Switching characteristics are measured using both VDD = 3 V and VDD = 5 V.
4 Propagation delay depends on the value of VDD, RPULL-UP, and CL.
5 Valid for commands that do not activate the RDY pin.
6 The RDY pin is low only for Command 2, Command 3, Command 8, Command 9, Command 10, and the PR hardware pulse: CMD_8 > 1 ms; CMD_9, CMD_10 > 0.12 ms;
CMD_2, CMD_3 > 20 ms. Device operation at TA = −40°C and VDD < 3 V extends the save time to 35 ms.
7 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117, and measured at −40°C, +25°C, and +85°C; typical endurance at 25°C is 700,000 cycles.
8 Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV
derates with junction temperature, as shown in Figure 45 in the Flash/EEMEM Reliability section.
Rev. B | Page 5 of 32
5 Page 
0
CODE 0x20
–6
0x10
–12
0x08
–18
0x04
–24
0x02
–30
0x01
–36
–42
100
1k 10k 100k
FREQUENCY (Hz)
1M
Figure 17. Gain vs. Frequency vs. Code, RAB = 50 kΩ (Figure 31)
0
CODE 0x20
–6
0x10
–12
0x08
–18
0x04
–24
0x02
–30
0x01
–36
–42
100
1k 10k
FREQUENCY (Hz)
100k
1M
Figure 18. Gain vs. Frequency vs. Code, RAB = 100 kΩ ( Figure 31)
80
RAB = 100kΩ
70
RAB = 50kΩ
60
50 RAB = 10kΩ
40
30
20
10
VDD = 5V ±100mV AC
VSS = 0V, VA = 5V, VB = 0V
MEASURED AT VW WITH CODE = 0x200
0
100
1k 10k 100k
1M
FREQUENCY (Hz)
Figure 19. PSRR vs. Frequency
10M
AD5233
VDD = 5V
VA = 2.25V
VB = 0V
100µs/DIV
VA
EXPECTED
VALUE
MIDSCALE
VW
0.5V/
DIV
Figure 20. Power-On Reset, VA = 2.25 V, VB = 0 V,
Code = 101010
2.60
2.58
2.56
2.54
2.52
2.50
2.48
2.46
2.44
2.42
2.40 0
VDD = VA = 5V
VSS = VB = 0V
CODE = 0x20 TO 0x1F
50 100 150 200 250 300 350 400 450 511
TIME (µs)
Figure 21. Midscale Glitch Energy, Code 0x20 to Code 0x1F
5V/DIV
CS
5V/DIV
CLK
5V/DIV
SDI
4ms/DIV
IDD
20mA/
DIV
Figure 22. IDD vs. Time When Storing Data to EEMEM
Rev. B | Page 11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD5233.PDF ] | |
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