|
|
PDF AD7265 Data sheet ( Hoja de datos )
| Número de pieza | AD7265 | |
| Descripción | Differential Input/ Dual 1 MSPS/ 12-Bit/ 3-Channel SAR ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD7265 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
Preliminary Technical Data
FEATURES
Dual 12-bit, 3-channel ADC
Fast throughput rate: 1 MSPS
Specified for VDD of 2.7 V to 5.25 V
Low power: 7 mW max at 1 MSPS with 3 V supplies
16.5 mW max at 1 MSPS with 5 V supplies
Wide input bandwidth
70 dB SNR at 100 kHz input frequency
On-chip reference: 2.5 V
–40°C to +125°C operation
Flexible power/throughput rate management
Simultaneous conversion/read
No pipeline delays
High speed serial interface SPI®/QSPI™/MICROWIRE™/DSP
compatible
Shutdown mode: 1 µA max
32-lead LFCSP and TQFP packages
GENERAL DESCRIPTION
The AD7265 is a dual, 12-bit, high speed, low power, successive
approximation ADC that operates from a single 2.7 V to 5.25 V
power supply and features throughput rates up to 1 MSPS. The
device contains two ADCs, each preceded by a 3-channel multi-
plexer, and a low noise, wide bandwidth track-and-hold amplifier
that can handle input frequencies in excess of 10 MHz.
The conversion process and data acquisition are controlled using
standard control inputs, allowing easy interfacing to microproces-
sors or DSPs. The input signal is sampled on the falling edge of CS;
conversion is also initiated at this point. The conversion time is
determined by the SCLK frequency. There are no pipelined delays
associated with the part.
The AD7265 uses advanced design techniques to achieve very low
power dissipation at high throughput rates. With 5 V supplies and a
1 MSPS throughput rate, the part consumes ? mA maximum. The
part also offers flexible power/throughput rate management when
operating in sleep mode.
The analog input range for the part can be selected to be a 0 V to
VREF range or a 2VREF range with either straight binary or twos
complement output coding. The AD7265 has an on-chip 2.5 V
reference that can be overdriven if an external reference is pre-
ferred. This external reference range is 100 mV to 2.5 V. The
AD7265 is available in 32-lead lead frame chip scale (LFCSP) and
thin flat quad (TQFP) lead package.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Differential Input, Dual 1 MSPS,
12-Bit, 3-Channel SAR ADC
AD7265
VA1
VA2
VA3
VA4
VA5
VA6
VB1
V
B2
VB3
VB4
VB5
VB6
FUNCTIONAL BLOCK DIAGRAM
REF SELECT
DcapA
AVdd DVdd
REF
BUF
MUX
T/H
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
AD7265
OUTPUT
DRIVERS
CONTROL
LOGIC
12-BIT
T/H SUCCESSIVE
APPROXIMATION
MUX
ADC
OUTPUT
DRIVERS
DOUTA
SCLK
+5
RANGE
DIFF/SE
A0
A1
A2
VDRIVE
DOUTB
BUF
AGND AGND AGND DcapB
DGND
DGND
Figure 1
PRODUCT HIGHLIGHTS
1. The AD7265 features two complete ADC functions that allow
simultaneous sampling and conversion of two channels. Each
ADC has 2 analog inputs, 3 fully differential pairs, or 6 single-
ended channels as programmed. The conversion result of both
channels is available simultaneously on separate data lines, or
in succession on one data line if only one serial port is
available.
2. High Throughput with Low Power Consumption
The AD7265 offers a 1 MSPS throughput rate with ? mW
maximum power consumption when operating at 3 V.
3. Flexible Power/Throughput Rate Management
The conversion rate is determined by the serial clock, allowing
power consumption to be reduced as conversion time is re-
duced through an SCLK frequency increase. Power efficiency
can be maximized at lower throughput rates if the part enters
sleep between conversions.
4. No Pipeline Delay
The part features two standard successive approximation
ADCs with accurate control of the sampling instant via a CS
input and once off conversion control.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 3. AD7265 Stress Ratings
Parameter
Rating
VDD to AGND
DVDD to DGND
VDRIVE to DGND
VDRIVE to AGND
AVDD to DVDD
AGND to DGND
Analog Input Voltage to AGND
Digital Input Voltage to DGND
Digital Output Voltage to GND
VREF to AGND
Input Current to Any Pin Except
Supplies1
–0.3 V to +7 V
–0.3 V to +7 V
–0.3 V to DVDD
–0.3 V to AVDD
–0.3 V to +0.3 V
–0.3 V to +0.3 V
–0.3 V to AVDD +0.3 V
–0.3 V to +7 V
–0.3 V to VDRIVE +0.3 V
–0.3 V to AVDD +0.3 V
±10 mA
Operating Temperature Range
–40°C to +125°C
Storage Temperature Range
Junction Temperature
LFCSP Package
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
–65°C to +150°C
150°C
108.2°C/W
32.71°C/W
TBD°C/W
Reflow Temperature (10- 30 sec)
TBD°C
ESD TBD
1 Transient currents of up to 100 mA will not cause SCR latch up.
AD7265
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrA | Page 5 of 16
5 Page 
Preliminary Technical Data
ANALOG INPUT
The analog inputs of the AD7265 may be configured as single
ended or true differential via the SGL/DIFF logic pin, as shown
in Figure 5. On the falling edge of CS, point A, the logic level of
the SGL/DIFF pin is checked to determine the configuration of
the analog input channels for the next conversion. If this pin is
tied to a logic low, the analog input channels to each on-chip
ADC are set up as three true differential pairs. If this pin is at a
logic high when CS goes low, the analog input channels to each
on-chip ADC are set up as six single-ended analog inputs. In
Figure 5 at point A, the SGL/DIFF pin is at a logic high so the
analog inputs are configured as single-ended for the next
conversion, i.e. sampling point B. At point B, the logic level of
the SGL/DIFF pin has changed to low; there fore, the analog
inputs are configured as differential for the next conversion
after this one, even though this current conversion is on single
ended configured inputs.
CS
SCLK
SGL/DIFF
A
1
14
B
1
14
Figure 5. Selecting Differential or Single Ended Configuration
AD7265
The channels to be converted on simultaneously are selected via
the multiplexer address inputs A0 to A2. The logic states of
these pins are also checked upon the falling edge of CS and the
channels are chosen for the next conversion. The selected input
channels are decoded as shown in Table 6.
The analog input range of the AD7265 can be selected as 0 V to
VREF or 0 V to 2 × VREF via the RANGE pin. This selection is
made in a similar fashion to that of the SGL/DIFF pin by
checking the logic state of the RANGE pin upon the falling edge
of CS. The analog input range is set up for the next conversion.
If this pin is tied to a logic low upon the falling edge of CS, the
analog input range for the next conversion is 0 V to VREF. If this
pin is tied to a logic high upon the falling edge of CS, the analog
input range for the next conversion is 0 V to 2 × VREF.
OUTPUT CODING
The AD7265 output coding is set to either twos complement or
straight binary depending on which analog input configuration
is selected for a conversion. Table 5 shows which output coding
scheme is used for each possible analog input configuration.
Table 5 AD7265 Output Coding
SGL/DIFF
Range
DIFF
0 V to VREF
DIFF
0 V to 2 × VREF
SGL 0 V to VREF
SGL 0 V to 2 × VREF
PSUEDO DIFF
0 V to VREF
PSUEDO DIFF
0 V to 2 × VREF
Output Coding
Twos Complement
Twos Complement
Straight Binary
Twos Complement
Straight Binary
Straight Binary
Table 6. Analog Input Type and Channel Selection
SGL/DIFF
1
1
1
1
1
1
0
0
0
0
0
0
A2 A1 A0 VIN+
0 0 0 VA1
0 0 1 VA2
0 1 0 VA3
0 1 1 VA4
1 0 0 VA5
1 0 1 VA6
0 0 0 VA1
0 0 1 VA1
0 1 0 VA3
0 1 1 VA3
1 0 0 VA5
1 0 1 VA5
ADC A
VIN–
AGND
AGND
AGND
AGND
AGND
AGND
VA2
VA2
VA4
VA4
VA6
VA6
ADC B
VIN+
VIN–
VB1 AGND
VB2 AGND
VB3 AGND
VB4 AGND
VB5 AGND
VB6 AGND
VB1 VB2
VB1 VB2
VB3 VB4
VB3 VB4
VB5 VB6
VB5 VB6
Comment
Single Ended
Single Ended
Single Ended
Single Ended
Single Ended
Single Ended
Fully Differential
Pseudodifferential
Fully Differential
Pseudodifferential
Fully Differential
Pseudodifferential
Rev. PrA | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD7265.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD7262 | Simultaneous Sampling SAR ADC | Analog Devices |
| AD7264 | Simultaneous Sampling SAR ADC | Analog Devices |
| AD7265 | Differential Input/ Dual 1 MSPS/ 12-Bit/ 3-Channel SAR ADC | Analog Devices |
| AD7266 | Differential Input/ Dual 2 MSPS/ 12-Bit/ 3-Channel SAR ADC | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |