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AD7228A 반도체 회로 부품 판매점

LC2MOS Octal 8-Bit DAC



Analog Devices 로고
Analog Devices
AD7228A 데이터시트, 핀배열, 회로
a
FEATURES
Eight 8-Bit DACs with Output Amplifiers
Operates with Single +5 V, +12 V or +15 V
or Dual Supplies
P Compatible (95 ns WR Pulse)
No User Trims Required
Skinny 24-Pin DlPs, SOIC, and 28-Terminal Surface
Mount Packages
LC2MOS
Octal 8-Bit DAC
AD7228A
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD7228A contains eight 8-bit voltage-mode digital-to-
analog converters, with output buffer amplifiers and interface
logic on a single monolithic chip. No external trims are required
to achieve full specified performance for the part.
Separate on-chip latches are provided for each of the eight D/A
converters. Data is transferred into the data latches through a
common 8-bit TTL/CMOS (5 V) compatible input port. Ad-
dress inputs A0, A1 and A2 determine which latch is loaded
when WR goes low. The control logic is speed compatible with
most 8-bit microprocessors.
Specified performance is guaranteed for input reference voltages
from +2 to +10 V when using dual supplies. The part is also
specified for single supply +15 V operation using a reference of
+10 V and single supply +5 V operation using a reference of
+1.23 V. Each output buffer amplifier is capable of developing
+10 V across a 2 kload.
The AD7228A is fabricated on an all ion-implanted, high-
speed, Linear Compatible CMOS (LC2MOS) process which has
been specifically developed to integrate high-speed digital logic
circuits and precision analog circuits on the same chip.
PRODUCT HIGHLIGHTS
1. Eight DACs and Amplifiers in Small Package
The single-chip design of eight 8-bit DACs and amplifiers al-
lows a dramatic reduction in board space requirements and
offers increased reliability in systems using multiple convert-
ers. Its pinout is aimed at optimizing board layout with all
analog inputs and outputs at one side of the package and all
digital inputs at the other.
2. Single or Dual Supply Operation
The voltage-mode configuration of the DACs allows single
supply operation of the AD7228A. The part can also be oper-
ated with dual supplies giving enhanced performance for
some parameters.
3. Microprocessor Compatibility
The AD7228A has a common 8-bit data bus with individual
DAC latches, providing a versatile control architecture for
simple interface to microprocessors. All latch enable signals
are level triggered and speed compatible with most high per-
formance 8-bit microprocessors.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703


AD7228A 데이터시트, 핀배열, 회로
AD7228A–SPECIFICATIONS
DUAL SUPPLY (VDD = 10.8 V to 16.5 V; VSS = –5 V ؎ 10%; GND = 0 V; VREF = +2 V to +10 V1; RL = 2 k, CL = 100 pF unless otherwise
noted.) All specifications TMIN to TMAX unless otherwise noted.
Parameter
STATIC PERFORMANCE
Resolution
Total Unadjusted Error3
Relative Accuracy
Differential Nonlinearity
Full-Scale Error4
Zero Code Error
@ 25°C
TMIN to TMAX
Minimum Load Resistance
REFERENCE INPUT
Voltage Range1
Input Resistance
Input Capacitance5
AC Feedthrough
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current
Input Capacitance5
Input Coding
DYNAMIC PERFORMANCE5
Voltage Output Slew Rate
Voltage Output Settling Time
Positive Full-Scale Change
Negative Full-Scale Change
Digital Feedthrough
Digital Crosstalk6
POWER SUPPLIES
VDD Range
VSS Range
IDD
@ 25°C
TMIN to TMAX
ISS
@ 25°C
TMIN to TMAX
B
Version2
8
±2
±1
±1
±1
± 25
± 30
2
2 to 10
2
500
–70
2.4
0.8
±1
8
Binary
2
5
5
50
50
10.8/16.5
–4.5/–5.5
16
20
14
18
CTU
Version Version Version
88
±1 ±2
± 1/2 ± 1
±1 ±1
± 1/2 ± 1
± 15 ± 25
± 20 ± 30
22
8
±1
± 1/2
±1
± 1/2
± 15
± 20
2
2 to 10
2
500
–70
2 to 10
2
500
–70
2 to 10
2
500
–7 0
2.4
0.8
±1
8
Binary
2.4
0.8
±1
8
Binary
2.4
0.8
±1
8
Binary
222
555
555
50 50 50
50 50 50
10.8/16.5 10.8/16.5 10.8/16.5
–4.5/–5.5 –4.5/–5.5 –4.5/–5.5
16 16 16
20 22 22
14 14 14
18 20 20
Units
Bits
LSB max
LSB max
LSB max
LSB max
mV max
mV max
kmin
V min/V max
kmin
pF max
dB typ
V min
V max
µA max
pF max
V/µs min
µs max
µs max
nV secs typ
nV secs typ
V min/V max
V min/V max
mA max
mA max
mA max
mA max
Conditions/Comments
VDD = +15 V ± 10%, VREF = +10 V
Guaranteed Monotonic
Typical tempco is 5 ppm/°C with VREF = +10 V
Typical tempco is 30 µV/°C
VOUT = +10 V
Occurs when each DAC is loaded with all 1s.
VREF = 8 V p-p Sine Wave @ 10 kHz
VIN = 0 V or VDD
VREF = +10 V; Settling Time to ± 1/2 LSB
VREF = +10 V; Settling Time to ± 1/2 LSB
Code transition all 0s to all 1s. VREF = 0 V; WR = VDD
Code transition all 0s to all 1s. VREF = +10 V; WR = 0 V
For Specified Performance
For Specified Performance
Outputs Unloaded; VIN = VINL or VINH
Outputs Unloaded; VIN = VINL or VINH
SINGLE SUPPLY (VDD = +15 V ؎ 10%, VSS; = GND = 0 V; VREF = +10 V, RL = 2 k, CL = 100 pF unless otherwise noted.)
AII specifications TMIN to TMAX unless otherwise noted.
STATIC PERFORMANCE
Resolution
Total Unadjusted Error3
Differential Nonlinearity
Minimum Load Resistance
8
±2
±1
2
888
±1 ±2 ±1
±1 ±1 ±1
222
Bits
LSB max
LSB max
kmin
Guaranteed Monotonic
VOUT = +10 V
REFERENCE INPUT
Input Resistance
Input Capacitance5
2 2 2 2 kmin
500 500 500 500 pF max
Occurs when each DAC is loaded with all 1s.
DIGITAL INPUTS
As per Dual Supply Specifications
DYNAMIC PERFORMANCE5
Voltage Output Slew Rate
Voltage Output Settling Time
Positive Full-Scale Change
Negative Full-Scale Change
Digital Feedthrough
Digital Crosstalk6
POWER SUPPLIES
VDD Range
IDD
@ 25°C
TMIN to TMAX
2
5
7
50
50
13.5/16.5
16
20
222
555
777
50 50 50
50 50 50
13.5/16.5 13.5/16.5 13.5/16.5
16 16 16
20 22 22
V/µs min
µs max
µs max
nV secs typ
nV secs typ
V min/V max
mA max
mA max
Settling Time to ± 1/2 LSB
Settling Time to ± 1/2 LSB
Code transition all 0s to all 1s. VREF = 0 V; WR = VDD
Code transition all 0s to all 1s. VREF = +10 V, WR = 0 V
For Specified Performance
Outputs Unloaded; VIN = VINL or VINH
NOTES
1VOUT must be less than VDD by 3.5 V to ensure correct operation.
2Temperature ranges are as follows:
B, C Versions; –40°C to +85°C
T, U Versions; –55°C to +125°C
3Total Unadjusted Error includes zero code error, relative accuracy and full-scale error.
4Calculated after zero code error has been adjusted out.
5Sample tested at 25°C to ensure compliance.
6The glitch impulse transferred to the output of one converter (not addressed) due to a
change in the digital input code to another addressed converter.
Specifications subject to change without notice.
–2– REV. A




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