AD722 판매점 - RGB to NTSC/PAL Encoder

AD722 반도체 회로 부품 판매점

RGB to NTSC/PAL Encoder

Analog Devices

RGB to NTSC/PAL Encoder

AD722

FEATURES

Low Cost, Integrated Solution

+5 V Operation

Accepts FSC Clock or Crystal, or 4FSC Clock

Composite Video and Separate Y/C (S-Video) Outputs

Minimal External Components:

No External Filters or Delay Lines Required

Onboard DC Restoration

Accepts Either HSYNC & VSYNC or CSYNC

Phase Lock to External Subcarrier

Drives 75 Ω Reverse-Terminated Loads

Logic Selectable NTSC or PAL Encoding Modes

Compact 16-Pin SOIC

APPLICATIONS

RGB to NTSC or PAL Encoding

PRODUCT DESCRIPTION

The AD722 is a low cost RGB to NTSC/PAL Encoder that

converts red, green and blue color component signals into their

corresponding luminance (baseband amplitude) and chromi-

nance (subcarrier amplitude and phase) signals in accordance

with either NTSC or PAL standards. These two outputs are

also combined to provide composite video output. All three out-

puts can simultaneously drive 75 Ω, reverse-terminated cables.

All logical inputs are CMOS compatible. The chip operates

from a single +5 V supply. No external delay lines or filters are

required. The AD722 may be powered down when not in use.

The AD722 accepts either FSC or 4FSC clock. When a clock is

not available, a low cost parallel-resonant crystal (3.58 MHz

(NTSC) or 4.43 MHz (PAL)) and the AD722’s on-chip oscilla-

tor generate the necessary subcarrier clock. The AD722 also ac-

cepts the subcarrier clock from an external video source.

The interface to VGA Controllers and MPEG Video Decoders

is simple: an on-chip logic “XNOR” accepts the available verti-

cal (VSYNC) and horizontal sync (HSYNC) signals and creates

the composite sync (CSYNC) signal on-chip. If available, the

AD722 will also accept a standard CSYNC signal by connecting

VSYNC to +5 V and applying CSYNC to HSYNC pin. The

AD722 contains decoding logic to identify valid HSYNC pulses

for correct burst insertion.

Delays in the U and V chroma filters are matched by an on-chip

sampled-data delay line in the Y signal path. To prevent

aliasing, a prefilter at 5 MHz is included ahead of the delay line

and a post-filter at 5 MHz is added after the delay line to sup-

press harmonics in the output. These low-pass filters are opti-

mized for minimum pulse overshoot. The overall luma delay,

relative to chroma, has been designed to be 170 ns, which

precompensates for delays in the filters used in the IF section of

a television receiver. This precompensation delay is already

present in TV broadcasts. The AD722 comes in a space-saving

SOIC and is specified for the 0°C to +70°C commercial tem-

perature range.

FUNCTIONAL BLOCK DIAGRAM

SUB-

CARRIER

FSC

4FSC

NTSC/PAL

HSYNC

VSYNC

XOSC

PHASE

DETECTOR

CHARGE

PUMP

FILTER

LOOP

4FSC

VCO

4FSC

XNOR

SYNC

SEPARATOR

FSC

BURST

CSYNC

NTSC/PAL

4FSC

CSYNC

QUADRATURE

DECODER

FSC 90°

FSC 0°

±180°

SC 90°/270°

(PAL ONLY)

BURST

NTSC/PAL

CLOCK

AT 4FSC

RED

CLAMP

GREEN

CLAMP

Y 3-POLE

LP PRE-

FILTER

RGB-TO-YUV

ENCODING

4-POLE

MATRIX

LPF

CLAMP

BLUE

CLAMP

V 4-POLE

LPF

CLAMP

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

CSYNC

INSERTION

SAMPLED-

DATA

DELAY

LINE

2-POLE

LP POST-

FILTER

NTSC/PAL

BALANCED

MODULATORS

3-POLE LPF

3.6MHz (NTSC)

4.4MHz (PAL)

LUMINANCE

OUTPUT

COMPOSITE

OUTPUT

CHROMINANCE

OUTPUT

One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.

Tel: 617/329-4700

Fax: 617/326-8703

AD722–SPECIFICATIONS (Unless otherwise noted, VS = +5, TA = +25°C, using FSC synchronous clock. All loads are

150 Ω ± 5% at the IC pins. Outputs are measured at the 75 Ω reverse terminated load.)

Parameter

SIGNAL INPUTS (RDIN, GRIN, BLIN)

Input Amplitude

Black Level

Input Resistance1

Input Capacitance

LOGIC INPUTS (SYNC, FSC, ENCD, NTSC)

Logic LO Input Voltage

Logic HI Input Voltage

Logic LO Input Current (DC)

Logic HI Input Current (DC)

VIDEO OUTPUTS2

Luminance (LUMA)

Roll-off @ 5 MHz

Gain Error

Linearity

Sync Level

DC Black Level

Conditions

NTSC

PAL

Red, Green, Blue

CMOS Logic Levels

NTSC

PAL

NTSC

PAL

Min Typ Max

714

700

–10

–7

–15 –5

+15

± 0.6

243 286 329

300

1.3

Chrominance (CRMA)

Bandwidth

Color Burst Amplitude

Color Signal to Burst Ratio Error

Color Burst Width

Phase Error3

DC Black Level

NTSC

PAL

NTSC

PAL

NTSC

PAL

3.6

4.4

170 240 330

252

–15 ± 3

2.51

2.28

±3

2.1

Chroma Feedthrough

Chroma/Luma Time Alignment

R, G, B = 0

10 40

–140

Composite (COMP)

Absolute Gain Error

Differential Gain

Differential Phase

DC Black Level

With Respect to Chroma

–5 ± 1

0.5

2.0

1.6

POWER SUPPLIES

Recommended Supply Range

Quiescent Current—Encode Mode

Quiescent Current—Power Down

Single Supply

+4.75

NOTES

1R, G, and B signals are inputted to an on-chip AC coupling capacitor.

2All outputs measured at a 75 Ω reverse-terminated load; voltages at the IC output pins are twice those specified here.

3Difference between ideal color-bar phases and the actual values.

Specifications are subject to change without notice.

+5.25

Units

mV p-p

MΩ

µA

MHz

mV p-p

µs

Degrees

mV p-p

–2– REV. 0

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AD722 data

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[ AD722.PDF ]

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AD722 반도체 회로 부품 판매점

RGB to NTSC/PAL Encoder

국내 전력반도체 판매점

일반적인 전자부품 판매점

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