파트넘버.co.kr AD6635 데이터시트 PDF


AD6635 반도체 회로 부품 판매점

4-Channel/ 80 MSPS WCDMA Receive Signal Processor (RSP)



Analog Devices 로고
Analog Devices
AD6635 데이터시트, 핀배열, 회로
4-Channel, 80 MSPS WCDMA
Receive Signal Processor (RSP)
AD6635
FEATURES
Four 80 MSPS Wideband Inputs (14 Linear Bits Plus 3 RSSI)
4 Real Input Ports/2 Complex Input Ports
Processes 4 Wideband Channels (UMTS or cdma2000
1x) or 8 GSM/EDGE, IS136 Channels
8 Independent Digital Receivers in a Single Package
Four 16-Bit Parallel Output Ports and Four 8-Bit Link Ports
4 Programmable Digital AGC Loops with 96 dB Range
Digital Resampling for Noninteger Decimation Rates
Programmable Decimating FIR Filters
4 Interpolating Half-Band Filters
Flexible Control for Multicarrier and Phased Array
Programmable Attenuator Control for Clip Prevention and
External Gain Ranging via Level Indicator
3.3 V I/O, 2.5 V CMOS Core
User Configurable Built-in Self Test (BIST) Capability
APPLICATIONS
Multicarrier, Multimode Digital Receivers
GSM, IS136, EDGE, PHS, IS95, UMTS, cdma2000
Micro and Pico Cell Systems, Software Radios
Wireless Local Loop
Smart Antenna Systems
In-Building Wireless Telephony
INA[13:0]
EXPA[2:0]
IENA
LIA-A
LIA-B
INB[13:0]
EXPB[2:0]
IENB
LIB-A
LIB-B
I
N
P
U
T
M
A
T
R
I
X
INC[13:0]
EXPC[2:0]
IENC
LIB-A
LIB-B
IND[13:0]
EXPD[2:0]
IEND
LID-A
LID-B
SYNCA
SYNCB
SYNCC
SYNCD
I
N
P
U
T
M
A
T
R
I
X
EXTERNAL
SYNC.
CIRCUIT
FUNCTIONAL BLOCK DIAGRAM
NCO
NCO
NCO
rCIC2
RESAMPLER
CIC5
rCIC2
RESAMPLER
CIC5
rCIC2
RESAMPLER
CIC5
rCIC2
RESAMPLER
CIC5
NCO
NCO
NCO
NCO
rCIC2
RESAMPLER
CIC5
rCIC2
RESAMPLER
CIC5
rCIC2
RESAMPLER
CIC5
rCIC2
RESAMPLER
CIC5
NCO
CLK
RSP
CLK
RAM
COEFFICIENT
FILTER
CHANNEL 0
RAM
COEFFICIENT
FILTER
CHANNEL 1
RAM
COEFFICIENT
FILTER
CHANNEL 2
RAM
COEFFICIENT
FILTER
CHANNEL 3
RAM
COEFFICIENT
FILTER
CHANNEL 4
RAM
COEFFICIENT
FILTER
CHANNEL 5
RAM
COEFFICIENT
FILTER
CHANNEL 6
RAM
COEFFICIENT
FILTER
CHANNEL 7
BUILT-IN (BIST)
SELF-TEST CIRCUITRY
TO A AND B
OUTPUT
PORTS
RCF OUTPUTS
CHANNELS 0, 1, 2,3
TO A AND B
OUTPUT
PORTS
CH A INTERPOLATING
HALF-BAND FILTER,
INTERLEAVING & AGC
TO A AND B
OUTPUT
PORTS
CH B INTERPOLATING
HALF-BAND FILTER,
INTERLEAVING & AGC
TO A AND B
OUTPUT
PORTS
RCF OUTPUTS
CHANNELS 0, 1, 2,3
PORT A
LINK PORT
OR
PARALLEL
PORT
CH A AND B
OUTPUT MUX
CIRCUITRY
PORT B
LINK PORT
OR
PARALLEL
PORT
TO C AND D
OUTPUT
PORTS
RCF OUTPUTS
CHANNELS 4, 5, 6,7
TO C AND D
OUTPUT
PORTS
CH C INTERPOLATING
HALF-BAND FILTER,
INTERLEAVING & AGC
TO C AND D
OUTPUT
PORTS
CH D INTERPOLATING
HALF-BAND FILTER,
INTERLEAVING & AGC
TO C AND D
OUTPUT
PORTS
RCF OUTPUTS
CHANNELS 4, 5, 6,7
MICROPORT OR SERIAL
PORT CONTROL
PORT C
8-BIT DSP
LINK PORT
OR
16-BIT
PARALLEL
OUTPUT
CH C AND D
OUTPUT MUX
CIRCUITRY
PORT D
8-BIT DSP
LINK PORT
OR
16-BIT
PARALLEL
OUTPUT
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.


AD6635 데이터시트, 핀배열, 회로
AD6635
GENERAL DESCRIPTION
The AD6635 is a multimode, 8-channel, digital Receive Signal
Processor (RSP) capable of processing up to four WCDMA
channels. Each channel consists of four cascaded signal-process-
ing elements: a frequency translator, two CIC decimating filters,
and a programmable coefficient-decimating filter. Each input
port has input level threshold detection circuitry for accommo-
dating large dynamic ranges or situations where gain ranging
converters are used. Quad 16-bit parallel output ports accom-
modate high data rate WBCDMA applications. On-chip
interpolating half-band filters can also be used to further
increase the output rate. In addition, each output port has a
digital AGC for accommodating large dynamic ranges using
smaller bit widths. The AGCs can maintain either signal level or
clipping level, depending on their mode. Link port outputs are
provided to enable glueless interfaces to Analog Devices’
TigerSHARC DSP core.
The AD6635 is part of Analog Devices’ SoftCell Multicarrier
transceiver chipset designed for compatibility with Analog Devices’
family of high sample rate IF sampling ADCs (AD9238/AD6645
12-bit and 14-bit). The SoftCell receiver comprises a digital
receiver capable of digitizing an entire spectrum of carriers and
digitally selecting the carrier of interest for tuning and channel
selection. This architecture eliminates redundant radios in wireless
base station applications.
High dynamic range decimation filters offer a wide range of
decimation rates. The RAM-based architecture allows easy
reconfiguration for multimode applications.
The decimating filters remove unwanted signals and noise from
the channel of interest. When the channel of interest occupies
less bandwidth than the input signal, this rejection of out-of-band
noise is called “processing gain.” By using large decimation
factors, processing gain can improve the SNR of the ADC by
30 dB or more. In addition, the programmable RAM coefficient
filter allows antialiasing, matched filtering, and static equaliza-
tion functions to be combined in a single, cost-effective filter.
Half-band interpolating filters at the output are used in various
applications, especially in WCDMA or cdma2000 applications,
to increase the output rate from 2¥ to 4¥ the chip rate. The
AD6635 is equipped with four independent automatic gain
control (AGC) loops for direct interface to a RAKE receiver.
The AD6635 is compatible with standard ADC converters, such
as the AD664x, AD943x, AD923x, and the AD922x families of
data converters. The AD6635 is also compatible with the
AD6600 Diversity ADC, and hence can be designed into exist-
ing systems that use AD6600 ADCs.
–2– REV. 0




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