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PDF AD6620 Data sheet ( Hoja de datos )
| Número de pieza | AD6620 | |
| Descripción | 65 MSPS Digital Receive Signal Processor | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
High Input Sample Rate
65 MSPS Single Channel Real
32.5 MSPS Diversity Channel Real
32.5 MSPS Single Channel Complex
NCO Frequency Translation
Worst Spur Better than –100 dBc
Tuning Resolution Better than 0.02 Hz
2nd Order Cascaded Integrator Comb FIR Filter
Linear Phase, Fixed Coefficients
Programmable Decimation Rates: 2, 3 . . . 16
5th Order Cascaded Integrator Comb FIR Filter
Linear Phase, Fixed Coefficients
Programmable Decimation Rates: 1, 2, 3 . . . 32
Programmable Decimating RAM Coefficient FIR Filter
Up to 130 Million Taps per Second
256 20-Bit Programmable Coefficients
Programmable Decimation Rates: 1, 2, 3 . . . 32
Bidirectional Synchronization Circuitry
Phase Aligns NCOs
Synchronizes Data Output Clocks
Serial or Parallel Baseband Outputs
Pin Selectable Serial or Parallel
Serial Works with SHARC, ADSP-21xx, Most Other
DSPs
16-Bit Parallel Port, Interleaved I and Q Outputs
Two Separate Control and Configuration Ports
Generic P Port, Serial Port
3.3 V Optimized CMOS Process
JTAG Boundary Scan
GENERAL DESCRIPTION
The AD6620 is a digital receiver with four cascaded signal-
processing elements: a frequency translator, two fixed-
coefficient decimating filters, and a programmable coefficient
decimating filter. All inputs are 3.3 V LVCMOS compatible.
All outputs are LVCMOS and 5 V TTL compatible.
As ADCs achieve higher sampling rates and dynamic range, it
becomes increasingly attractive to accomplish the final IF stage
of a receiver in the digital domain. Digital IF Processing is less
expensive, easier to manufacture, more accurate, and more
flexible than a comparable highly selective analog stage.
The AD6620 diversity channel decimating receiver is designed
to bridge the gap between high speed ADCs and general pur-
pose DSPs. The high resolution NCO allows a single carrier to
be selected from a high speed data stream. High dynamic range
decimation filters with a wide range of decimation rates allow
65 MSPS Digital Receive
Signal Processor
AD6620
FUNCTIONAL BLOCK DIAGRAM
REAL,
DUAL REAL,
OR COMPLEX
INPUTS
COS
I II
CIC FIR OUTPUT
Q FILTERS Q FILTER Q FORMAT
SERIAL OR
PARALLEL
OUTPUTS
–SIN
COMPLEX
NCO
EXTERNAL
SYNC
CIRCUITRY
JTAG
PORT
P
OR SERIAL
CONTROL
both narrowband and wideband carriers to be extracted. The
RAM-based architecture allows easy reconfiguration for multi-
mode applications.
The decimating filters remove unwanted signals and noise from
the channel of interest. When the channel of interest occupies
less bandwidth than the input signal, this rejection of out-of-
band noise is called “processing gain.” By using large decima-
tion factors, this “processing gain” can improve the SNR of the
ADC by 36 dB or more. In addition, the programmable RAM
Coefficient filter allows antialiasing, matched filtering, and
static equalization functions to be combined in a single, cost-
effective filter.
The input port accepts a 16-bit Mantissa, a 3-bit Exponent,
and an A/B Select pin. These allow direct interfacing with the
AD6600, AD6640, AD9042 and most other high speed ADCs.
Three input modes are provided: Single Channel Real, Single
Channel Complex, and Diversity Channel Real.
When paired with an interleaved sampler such as the AD6600,
the AD6620 can process two data streams in the Diversity
Channel Real input mode. Each channel is processed with co-
herent frequency translation and output sample clocks. In addi-
tion, external synchronization pins are provided to facilitate
coherent frequency translation and output sample clocks among
several AD6620s. These features can ease the design of systems
with diversity antennas or antenna arrays.
Units are packaged in an 80-lead PQFP (plastic quad flatpack)
and specified to operate over the industrial temperature range
(–40°C to +85°C).
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
1 page  
TIMING CHARACTERISTICS (CLOAD = 40 pF All Outputs)
Parameter (Conditions)
Temp
Test
Level
Min
AD6620AS
Typ
CLK Timing Requirements:
tCLK
tCLKL
tCLKH
CLK Period
CLK Width Low
CLK Width High
Full I
Full IV
Full IV
15.4
7.0
7.0
0.5 × tCLK
0.5 × tCLK
Reset Timing Requirements:
tRESL
RESET Width Low
Full I
30.0
Input Data Timing Requirements:
tSI Input1 to CLK Setup Time
tHI Input1 to CLK Hold Time
Full IV
Full IV
–1.0
6.5
Parallel Output Switching Characteristics:
tDPR CLK to OUT[15:0] Rise Delay
tDPF CLK to OUT[15:0] Fall Delay
tDPR CLK to DVOUT Rise Delay
tDPF CLK to DVOUT Fall Delay
tDPR CLK to IQOUT Rise Delay
tDPF CLK to IQOUT Fall Delay
tDPR CLK to ABOUT Rise Delay
tDPF CLK to ABOUT Fall Delay
SYNC Timing Requirements:
tSY SYNC2 to CLK Setup Time
tHY SYNC2 to CLK Hold Time
SYNC Switching Characteristics:
tDY CLK to SYNC3 Delay Time
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full V
8.0
7.5
6.5
5.5
7.0
6.0
7.0
5.5
–1.0
6.5
7.0
Serial Input Timing:
tSSI
tHSI
tHSRF
tSSF
tHSF
SDI to SCLKt Setup Time
SDI to SCLKt Hold Time
SDFS to SCLKu Hold Time
SDFS to SCLKt Setup Time4
SDFS to SCLKt Hold Time4
Serial Frame Output Timing:
tDSE SCLKu to SDFE Delay Time
tSDFEH
tDSO
SDFE Width High
SCLKu to SDO Delay Time
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full V
Full IV
1.0
2.0
4.0
1.0
2.0
3.5
4.5
tSCLK
SCLK Switching Characteristics, SBM = “1”:
tSCLK
SCLK Period3
tSCLKL
SCLK Width Low
tSCLKH
SCLK Width High
tSCLKD
CLK to SCLK Delay Time
Serial Frame Timing, SBM = “1”:
tDSF SCLKu to SDFS Delay Time
tSDFSH
SDFS Width High
SCLK Timing Requirements, SBM = “0”:
tSCLK
tSCLKL
tSCLKH
SCLK Period
SCLK Width Low
SCLK Width High
Full I
Full V
Full V
Full V
Full IV
Full V
Full I
Full IV
Full IV
2 × tCLK
6.5
0.5 × tSCLK
0.5 × tSCLK
1.0
15.4
0.4 × tSCLK
0.4 × tSCLK
tSCLK
0.5 × tSCLK
0.5 × tSCLK
NOTES
1Specification pertains to: IN[15:0], EXP[2:0], A/B.
2Specification pertains to: SYNC_NCO, SYNC_CIC, SYNC_RCF.
3SCLK period will be ≥ 2 × tCLK when AD6620 is Serial Bus Master (SBM = 1) depending on the SDIV word.
4SDFS setup and hold time must be met, even when configured as outputs, since internally the signal is sampled at the pad.
Specifications subject to change without notice.
AD6620
Max
19.5
19.5
19.0
11.5
19.5
13.5
19.5
13.5
23.5
11.0
11.0
13.0
4.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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–5–
5 Page 
AD6620
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.5 V
Input Voltage . . . . –0.3 V to VDD + 0.3 V (Not 5 V Tolerant)
Output Voltage Swing . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . +130°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . .+280°C
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only; functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Thermal Characteristics
80-Lead Plastic Quad Flatpack:
θJA = 44°C/Watt
EXPLANATION OF TEST LEVELS
I. 100% Production Tested.
II. 100% Production Tested at +25°C, and Sampled Tested at
Specified Temperatures.
III. Sample Tested Only.
IV. Parameter Guaranteed by Design and Analysis.
V. Parameter is Typical Value Only.
VI. 100% Production Tested at +25°C, and Sampled Tested at
Temperature Extremes.
Model
AD6620AS
AD6620S/PCB
ORDERING GUIDE
Temperature Range
–40°C to +85°C (Ambient)
Package Description
80-Lead PQFP (Plastic Quad Flatpack)
Evaluation Board with AD6620AS and Software
Package
Option
S-80A
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6620 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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–11–
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD6620.PDF ] | |
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