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PDF AK2303LV Data sheet ( Hoja de datos )
| Número de pieza | AK2303LV | |
| Descripción | Dual PCM CODEC for PBX Analog Line Card | |
| Fabricantes | Asahi Kasei Microsystems | |
| Logotipo |  |
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ASAHI KASEI
[AK2303LV]
AK2303LV
Dual PCM CODEC for PBX Analog Line Card
GENERAL DESCRIPTION
AK2303LV is a 3.3V dual PCM CODEC-Filter most
suitable for analog line card of PBX switch.
CODEC-Filter is compliant with G711/G712
recommendations.
It includes Selectable A-law/u-law function, Internal
Gain Adjustment from +6dB to –18dB by 1dB step
control. All of these functions are controlled by the
internal register accessed through the serial interface.
Additionally, channel mute and A-law/u-law selection is
controlled by the hard pin.
PCM interface of AK2303LV supports Long Frame,
Short Frame clock formats and GCI format. 4.096MHz,
2.048MHz bit clock input is available for PCM interface.
FEATURE
- Dual PCM CODEC and Filtering systems for
PBX switch
- Independent functions on each channel
Controlled by the internal register or hard pin
- Power Down Mode (Register setting)
- Mute (Hard pin, register setting)
- Gain Adjustment: +6 to -18dB (1dB step by
register setting)
- Selectable PCM Data Interface Timing:
Long Frame / Short Frame/GCI
- Selectable PCM Data Rate:
4.096MHz, 2.048MHz (Register setting)
- OP Amp for External Gain Adjustment
- A-law/u-law Select (Hard pin, Register setting)
- Serial Interface for the internal register access
- Power on Reset
- Single Power Supply Voltage
- +3.3V ± 0.3V
- Low Power Consumption
- 35mW typ
PACKAGE
- 28pinVSOP
9.8 x 7.6 mm (0.65mm pin pitch)
MS0117-E-00
1
2001/09
1 page  
ASAHI KASEI
PIN CONDITION
[AK2303LV]
Pin
#
Name
I/O
Pin type
AC load
(MAX.)
DC load
(MIN.)
Outout status
(Power down
mode)
Remarks
1 TEST
I
(*2)
Tied to AVSS
2 VFTN1
I
Analog
3 GST1 O Analog
50pF
10kΩ(*1)
Hi-Z
4 GSR1 O Analog
50pF
10kΩ(*1)
Hi-Z
5 VFR1 I Analog
6 VR1
O Analog
50pF
10kΩ
Hi-Z
7 ALAWN
I
CMOS
8 AVDD
－
9 DVDD
－
10 FS
I CMOS
11 BCLK I CMOS
12 DX
O CMOS
15pF
Hi-Z
13 DR
I CMOS
14 MUTE1
I
CMOS
15 MUTE0
I
CMOS
16 SCLK I CMOS
17 DATA I/O CMOS
15pF
Hi-Z (Input)
18 CSN
I CMOS
19 LPC
O Analog
0.22uF
20 VR0
O Analog
50pF
10kΩ
Hi-Z
21 DVSS
－
22 AVSS
－
23 VFR0 I Analog
24 GSR0 O Analog
50pF
10kΩ(*1)
Hi-Z
25 GST0 O Analog
50pF
10kΩ(*1)
Hi-Z
26 VFTN0
I
Analog
27 MODE
I
(*2)
Tied to AVSS or
AVDD
28 VREF O Analog
More than 1.0uF
*1) DC load(MIN.) includes a feedback resistance of input/output op-amp.
*2) Please tie to AVSS or AVDD, in order not to have a noise impact to the adjacent analog pins.
2303-E-00
5 2001/09
5 Page 
ASAHI KASEI
Long Frame
[AK2303LV]
FS
BCLK
DX
B1 ch
1 2 3 4 5 6 78
B2 ch
1 2 3 4 5 6 78
DR
Don’t
care
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
SEL2B=0 ⇒
SEL2B=1 ⇒
B1-CHANNEL (CH0)
B1-CHANNEL (CH1)
B2-CHANNEL (CH1)
B2-CHANNEL (CH0)
Short Frame
Don’t care
FS
BCLK
DX
B1 ch
1 2 3 4 5 6 78
B2 ch
1 2 3 4 5 6 78
DR
Don’t
care
1234567812345678
SEL2B=0 ⇒
SEL2B=1 ⇒
B1-CHANNEL (CH0)
B1-CHANNEL (CH1)
B2-CHANNEL (CH1)
B2-CHANNEL (CH0)
Don’t care
! Important Notice
Please set time-slot selection as proper value. Maximum time slot is determined from clock speed.
At the power up sequence, please set the mute by MUTE0/1 before power up.
Then release them after the CODEC initialization and TS assignment to avoid the PCM output data collision with other
CODEC’s PCM output.
Please don’t stop feeding FS and BCLK except in Full power down mode.
Internal PLL does free running when BCLK is not provided.
2303-E-00
11 2001/09
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AK2303LV.PDF ] | |
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