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PDF ADV7202 Data sheet ( Hoja de datos )
| Número de pieza | ADV7202 | |
| Descripción | Simultaneous Sampling Video Rate Codec | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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PRELIMINARY TECHNICAL DATA
a
Simultaneous Sampling
Video Rate Codec
Preliminary Technical Data
ADV7202
FEATURES
Four 10-Bit Video DACs (4:2:2, YCrCb, RGB I/P
Supported)
10-Bit Video Rate Digitization at Up to 54 Mhz
AGC Control (؎6 dB)
Front-End 3-Channel Clamp Control
Up to Five CVBS Input Channels, Two Component YUV,
Three S-Video, or a combination of the above. Simul-
taneous Digitization of Two CVBS Input Channels.
Aux 8-Bit SAR ADC @ 843 kHz Sampling Giving up to
Eight General Purpose Inputs
I2C and SPI Compatible Interface with I2C Filter
RGB Inputs for Picture-on-Picture of the RGB DACs
APPLICATIONS
Picture-on-Picture Video Systems
Simultaneous Video Rate Processing
Hybrid Set-Top Box TV Systems
Direct Digital Synthesis/I-Q Demodulation
Image Processing
GENERAL DESCRIPTION
The ADV7202 is a video rate sampling Codec.
It has the capability of sampling up to five NTSC/PAL/SECAM
video I/P signals. The resolution on the front-end digitizer is
12 bits; 2 bits (12 dB) are used for gain and offset adjustment.
The digitizer has a conversion rate of 54 MHz.
It also has up to eight auxiliary inputs that can be sampled by
an 843 kHz SAR ADC for system monitoring, etc.
The back end consists of four 10-bit DACs that run at up to
54 MHz and can be used to output CVBS, S-Video, Component
YCrCb, and RGB.
This Codec also supports Picture-on-Picture with the 3-channel
I/P mux that also muxes to the DAC O/Ps.
The ADV7202 can operate at 3.3 V or 5 V. Its monolithic CMOS
construction ensures greater functionality with lower power
dissipation.
The ADV7202 is packaged in a small 64-lead LQFP package.
FUNCTIONAL BLOCK DIAGRAM
DOUT DAC DATA
XTAL [9:0]
[9:0]
OSD I/P "S"
AIN1P
AIN1M
AIN2P
AIN2M
AIN3P
AIN3M
AIN4P
AIN4M
AIN5P
AIN5M
AIN6P
AIN6M
I/P
MUX
SHA AND
CLAMP
SHA AND
CLAMP
SHA AND
CLAMP
MUX
ADC BLOCK
12-BIT
A/D
A/D
8-BIT 843KHz
ADV7202
ADC
DAC
LOGIC LOGIC
10-BIT
D/A
10-BIT
D/A
10-BIT
D/A
10-BIT
D/A
12C/SPI
DAC0
DAC1
DAC2
DAC3
REV. PrB
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
1 page  
PRELIMINARY TECHNICAL DATA
ADV7202
3.3 V SPECIFICATIONS (AVDD/DVDD = 3.3 V ؎ 5%, VREF = 1.235 V RSET = 1.2 k⍀, all specifications TMIN to TMAX1 unless otherwise noted.)
Parameter
Min Typ Max
Unit
Test Conditions
STATIC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
VIDEO ADC
Resolution
Accuracy
Integral Nonlinearity
Differential Nonlinearity
Differential Input Voltage Range2
SNR
AUX ADC
Resolution
Differential Nonlinearity
Integral Nonlinearity
SNR
Input Voltage Range
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
DIGITAL OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current
Output Capacitance
Digital Output Access Time, t14
Digital Output Hold Time, t15
10 Bits
10
± 2 LSB
± 2 LSB
–VREFADC
10
10
±1
± 0.25
62
50
10 Bits
+VREFADC
LSB
LSB
dB
dB
Bits
± 1 LSB
± 2 LSB
44 dB
0 2 VREFADC V
2V
0.8 V
± 1 µA
10 pF
2.4
0.4
10
30
8
3
V
V
µA
pF
ns
ns
10-Bit Operation
10-Bit Operation
(Plus 2-Bits for gain ranging) 2.2 V Ref.
10-Bit
10-Bit
See Table II
27 MHz Clock, fIN = 100 kHz
54 MHz Clock, fIN = 100 kHz
Guaranteed Monotonic
27 MHz Clock
ISOURCE = 400 µA
ISINK = 3.2 mA
See Figure 16
ANALOG OUTPUTS
Output Current
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
Analog Output Delay3
DAC Output Skew
4.33 mA
2%
0 1.4 V
50 kΩ
30 pF
7 ns
0 ns
VOLTAGE REFERENCE
Reference Range, VREFDAC
Reference Range, VREFADC
1.235
1.100
V
V
NOTES
10°C to 70°C.
2SHA gain = 1, half range for SHA gain = 2, see Table II.
3Output delay measured from 50% of the rising edge of the clock to the 50% point of full scale transition.
Specifications subject to change without notice.
RSET = 1.2 kΩ, RL = 300 Ω
IOUT = 0 mA
REV. PrB
–5–
5 Page 
PRELIMINARY TECHNICAL DATA
ADV7202
Video Clamping and AGC Control
When Analog signal clamping is required the input signal should
be AC coupled to the input via a capacitor, the clamping control
is via the MPU port. The AGC is implemented digitally. For
correct operation the user must program the clamp value to which
the signal has been clamped into the ADV7202 I2C Register. This
allows the user to specify which signal level is unaffected by the
AGC. The digital output signal will be a function of the ADC
output, the AGC Gain, and the Clamp Level, and can be repre-
sented as follows,
[ ]( )D_OUT = ADC Gain × ADC – Clamp Level + Clamp Level (1)
D_OUT will be a 10-bit number (0–1023), the AGC Gain
defaults to 2 and can have a value between 0 to 7.99. The Clamp
Level is a 10-bit number (0–1023) although only the top eight
bits of clamp level are specified in the I2C Register; the ADC
value can be regarded as a 10-bit number (0–1023) for the
equation. It should be noted that the ADC resolution is 12 bits.
The above equation is used to give a basic perspective, and is
mathematically correct.
When the clamps are operational, the operation described by
Equation (1) is how the ADV7202 ensures that the level to
which the user is clamping is unaffected by the AGC loop.
When no clamps are operational, the operation should be
regarded as a straightforward gain-and-level shift.
Equation (1) maps the ADC input voltage range to its output.
AGC Gain
The AGC Gain can be set to a value from 0 to 7.9. The AGC
Gain Register holds a 12-bit number that corresponds to the
required gain. The first three MSBs hold the gain integer value
while the remaining nine bits hold the gain fractional value.
Example: The user requires a gain of 3.65.
The first three bits give the integer value 3, hence these will be
set to ‘0 1 1.’ The remaining nine bits will have to be set to give
the fractional value 0.65, 512 ϫ 0.65 = 333 = ‘10100110 1.’
From Equation (2) it can be seen that the Clamp Level is
taken from the signal before AGC is applied and then added on
again afterwards; hence, if the AGC Gain is set to a value of
one, the result would be as follows,
(AGC Gain = 1)
D_OUT = ADC - Clamp Level + Clamp Level = ADC (2)
FUNCTIONAL DESCRIPTION
Clamp and AGC Control
The ADV7202 has a front end 3-channel clamp control. In
order to perform an accurate AGC gain operation, it is neces-
sary to know to what level the user is clamping the black level;
this value is programmable in Clamp Register 0 CR00–CR07.
Each channel has a fine and coarse clamp; the clamp direction
and its duration are programmable. Synchronization of the clamps
and AGC to the input signal is possible using the SYNC_IN con-
trol pin and setting mode register CR14 to Logic Level “1.” Using
this method, it is possible to ensure that AGC and clamping are
only applied outside the active video area.
Control Signals
The function and operation of the SYNC_IN signal is described
in the Clamp Control section. The SYNC_OUT will go high
while Cr data from a YCrCb data stream or C data from a Y/C
data stream has been output on DOUT[9:0]. See Figure 1 to
Figure 3.
I2C Filter
A selectable internal I2C filter allows significant noise reduction
on the I2C interface. In setting ALSB high, the input bandwidth
on the I2C lines is reduced and pulses of less than 50 ns are not
passed to the I2C controller. Setting ALSB low allows greater
input bandwidth on the I2C lines.
XTAL0
DAC_DATA [9:0]
CVBS
CVBS
CVBS
CVBS
CVBS
CVBS
CVBS
SYNC_OUT
Figure 1. SYNC_OUT Output Timing, CVBS Input
XTAL0
DAC_DATA [9:0]
YCYC Y CY
SYNC_OUT
Figure 2. SYNC_OUT Output Timing, Y/C (S-VIDEO) Input
REV. PrB
–11–
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet ADV7202.PDF ] | |
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