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PDF 65C00 Data sheet ( Hoja de datos )
| Número de pieza | 65C00 | |
| Descripción | MICROPROCESSORS | |
| Fabricantes | Commodore | |
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~ aamiconcluct:ar group
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MPS
65COO
MICROPROCESSORS
65COO MICROPROCESSORS
THE 65COO MICROPROCESSOR FAMILY CONCEPT -
The 65COO Series Microprocessors represent the first totally software compatible microprocessor
family. This family of products includes a range of software compatible microprocessors which provide a
selection of addressable memory range, Interrupt input options and on-chip clock oscillators and drivers. All of
the microprocessors in the 65COO group are software compatible within the group and are bus compatible with
the M6800 product offering.
The family includes six microprocessors with on-board clock oscillators and drivers and four micropro-
cessors driven by external clocks. The on-chip clock versions are aimed at high performance, low cost
applications where single phase inputs, crystal or RC inputs provide the time base. The external clock versions
are geared for the multi processor system applications where maximum timing control is mandatory. All
versions of the microprocessors are available in 1 MHz maximum operating frequencies.
FEATURES OF THE 6500 FAMILY
• Single +5 volt supply
• Eight bit parallel processing
• 56 Instructions
• Decimal and binary arithmetic
• Thirteen addressing modes
• True indexing capability
• Programmable stack pOinter
• Variable length stack
• Interrupt capability
• Non-maskable interrupt
• Use with any type or speed memory
• 8 BIT Bi-directional Data Bus
• Addressable memory range of up to
65K bytes
• "Ready" input (for single cycle execution)
• Direct memory access capability
• Bus compatible with M6800
• Choice of external or on-board clocks
• 1 MHz operation
• On-the-chip clock options
*External single clock input
*RC time base input
*Crystal time base input
• Pipeline architecture
MEMBERS OF THE 65COO MICROPROCESSOR
(CPU) FAMILY
Microprocessors with On-Chip Clock Oscillator
Model
MPS65C02
MPS65C03
MPS65C04
MPS65C05
MPS65C06
MPS65C07
Addressable Memory
65K Bytes
4K Bytes
8K Bytes
4K Bytes
4K Bytes
8K Bytes
Microprocessors with External Two Phase
Clock Inputs
LMPS65C12
MPS65C13
MPS65C14
MPS65C15
65K Bytes
4K Bytes
8K Bytes
4K Bytes
ORDER NUMBER:
MXS65CXX
~ MODEL DESIGNATOR
xx = 02,03,04, ... 15
PACKAGE DESIGNATOR
=C CERAMIC
P = PLASTIC
3-2
1 page  
MPS
65COO
1 MHz TIMING
= = =Electrical Characteristics: Ncc 5V ± 5%, Vss 0 V, TA 0°-70°C)
CLOCK TIMING - 65C02, 03, 04, 05
CHARACTERISTIC
SYMBOL
MIN.
Cycle Time
00(1N) Pulse Width (measured at 1.5v)
¢O (IN) Rise, Fall Time
TCYC
PWH¢O
TR¢O,TF¢O
1000
460
-
OelayTime between Clocks (measured at 1.5v)
01 (OUn Pulse Width (measured at 1.5v)
TO
PWH~1
5
PWH¢OL-20
<iJ2(OUn Pulse Width (measured at 1.5v)
¢1 (OUn, ¢2(OUT) Rise, Fall Time
(measured .Bv to 2.0v)
(Load Y2 30pf 1/2 1 TIL)
PWH~2
TR,TF
PWH00H-40
-
TYP.
-
-
-
-
-
-
-
MAX.
-
520
10
-
PWH¢OL
PWH¢OH-10
25
CLOCK TIMING: 65C12, 13, 14, 15
CHARACTERISTIC
Cycle Time
Clock Pulse Width ¢1
(Measured at Vcc - 0.2v)
(2)2
Fall Time, Rise Time
(Measured from 0.2v to Vcc - 0.2v)
Delay Time between Clocks
(Measured at 0.2v)
SYMBOL
TCYC
PWH ~1
PWH ¢2
TF, TR
TO
MIN.
1000
430
470
-
0
TY~.
-
-
-
-
MAX.
-
-
25
-
REAO/ WRITE TIMING (LOAD = ITIL)
CHARACTERISTIC
Read/ Write Setup Time from 65COO
Address Setup Time from 65COO
Memory Read Access Time
Data Stability Time Period
Data Hold Time - Read
Data Hold Time - Write
Data Setup Time from 65COO
S.O. Setup Time
SYNC Setup Time from 6500
Address Hold Time
R/W Hold Time
ROY Setup Time
SYMBOL
TRWS
TAOS
TACC
TOSU
THR
THW
TMOS
TS.O.
TSYNC
THA
THRW
TROY
MIN.
-
-
-
100
10
30
-
100
-
30
30
100
TYP.
100
100
-
-
-
60
150
-
-
60
60
-
MAX.
300
300
575
-
-
-
200
-
350
-
-
-
3-6
5 Page 
C= ©~@@
VSS
!ll1(1N) c::
IRQ
NMI
vee
AO
A1
A2
A3
A4
AS
A6
A7
A8
RES
¢2(IN)
RNJ
DO
01
02
03
04
05
06
07
A11
A10
A9
vee
A1
A2
A3
A4
AS
A6
A7
AB
A9
RES
!ll2(IN)
R/W
DO
01
02
D3
04
os
06
07
A12
A11
A10
MPS
65COO
65C13 - 28 Pin Package
Features of 65C13
• 4K Addressable Bytes of Memory (AO-A11)
• Two phase clock Input
• IRQ Interrupt
• NMI Interrupt
• 8 Bit Bidirectional Data Bus
65C14 - 28 Pin Package
Features of 65C14
• 8K Addressable Bytes of Memory (AO·A12)
• Two phase clock input
• IRQ Interrupt
• 8 Bit Bidirectional Data Bus
VSS
IRQ
vee
AO
A1
A2
A3
A4
AS
AS
A7
A8
RES
¢2(1N)
RNJ
DO
01
02
03
04
OS
06
07
A11
A10
A9
65C15 - 28 Pin Package
Features of 65C15
• 4K Addressable Bytes of Memory (AO·A 11)
• Two phase clock input
• IRQ Interrupt
• ROY Signal
• 8 Bit Bidirectional Data Bus
COMMODORE SEMICONDUCTOR GROUP reserves the right to make changes to any products herein to
improve reliability,function or design. COMMODORE SEMICONDUCTOR GROUP does not assume any
liability arising out of the application or use of any product or circuit described herein; neither does it convey
any license under its patent rights nor the rights of others.
3-12
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet 65C00.PDF ] | |
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