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Número de pieza | R5F21324DNSP | |
Descripción | MCU | |
Fabricantes | Renesas | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de R5F21324DNSP (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! R8C/32D Group
RENESAS MCU
REJ03B0288-0100
Rev.1.00
Feb 26, 2010
1. Overview
1.1 Features
The R8C/32D Group of single-chip MCUs incorporates the R8C CPU core, employing sophisticated instructions
for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions at high
speed. In addition, the CPU core boasts a multiplier for high-speed operation processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs are
designed to maximize EMI/EMS performance.
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of
system components.
1.1.1 Applications
Electronic household appliances, office equipment, audio equipment, consumer equipment, etc.
REJ03B0288-0100 Rev.1.00 Feb 26, 2010
Page 1 of 42
1 page R8C/32D Group
1.3 Block Diagram
Figure 1.2 shows a Block Diagram.
1. Overview
I/O ports
Peripheral functions
Timers
Timer RA (8 bits × 1)
Timer RB (8 bits × 1)
Timer RC (16 bits × 1)
Timer RE (8 bits × 1)
Watchdog timer
(14 bits)
A/D converter
(10 bits × 4 channels)
8 4 31
Port P1
Port P3
Port P4
UART or
clock synchronous serial I/O
(8 bits × 2)
System clock generation
circuit
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
XCIN-XCOUT
Low-speed on-chip oscillator
for watchdog timer
Voltage detection circuit
Comparator B
Figure 1.2 Block Diagram
R8C CPU core
R0H R0L
R1H R1L
R2
R3
A0
A1
FB
SB
USP
ISP
INTB
PC
FLG
Memory
ROM (1)
RAM (2)
Multiplier
Notes:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
REJ03B0288-0100 Rev.1.00 Feb 26, 2010
Page 5 of 42
5 Page R8C/32D Group
2. Central Processing Unit (CPU)
2.8.7 Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
If necessary, set to 0. When read, the content is undefined.
REJ03B0288-0100 Rev.1.00 Feb 26, 2010
Page 11 of 42
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet R5F21324DNSP.PDF ] |
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