PDF XS1-G04B-FB144 Data sheet ( Hoja de datos )

Número de pieza	XS1-G04B-FB144
Descripción	MCU
Fabricantes	Xmos
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No Preview Available ! XS1-G04B-FB144 Datasheet Document Number: 1087D Publication Date: 2011/10/06 Copyright © 2010 XMOS Limited, All Rights Reserved. 1 page XS1-G04B-FB144 Datasheet 3 Signal Description 4 Module Power PLL JTAG XCore 0 I/O Signal Function Type Active Properties PU=Pull Up, PD=Pull Down, ST=Schmitt Trigger, OT=Output Tristate, S=Switchable VDD RS=Required for SPI boot (§5.8), RU=Required for USB-enabled devices (§10) Digital core power PWR — VSS Digital ground GND — IO VDD Digital I/O power PWR — SS_PLL_AGND Analog ground for PLL GND — SS_PLL_AVDD Analog PLL power PWR — OTP_VPP OTP programming voltage PWR — SS_RESET Global reset input Input — PU, ST SS_CLK PLL reference clock Input — PD, ST SS_PLL_BYPASS PLL bypass Input — PD SS_XC0_BS[0:0] Boot status (core 0) I/O — PU SS_TDI Test data input Input — PU, ST SS_TDO Test data output Output — PD SS_TMS Test mode select Input — PU, ST SS_TRST Test reset input Input — PU, ST SS_TCK Test clock Input — PU, ST SS_DEBUG Multi-chip debug I/O — PU X0D00 X0D01 X0D02 X0D03 X0D04 X0D05 X0D06 X0D07 X0D08 X0D09 X0D10 X0D11 X0D12 X0D13 X0D14 X0D15 X0D16 X0D17 X0D18 X0D19 X0D20 X0D21 P1A0 X0LA45ib P1B0 X0LA35ib P4A0 P8A0 P16A0 X0LA25ib P4A1 P8A1 P16A1 X0LA12bi /5b P4B0 P8A2 P16A2 X0LA02bi /5b P4B1 P8A3 P16A3 X0LA02bo/5b P4B2 P8A4 P16A4 X0LA12bo/5b P4B3 P8A5 P16A5 X0LA25ob P4A2 P8A6 P16A6 X0LA35ob P4A3 P8A7 P16A7 X0LA45ob P1C0 P1D0 P32A20 P32A21 P32A22 P32A23 P32A24 P32A25 P32A26 P32A27 P1E0 X0LB45ib P1F0 X0LB35ib P4C0 P8B0 P16A8 P32A28 X0LB25ib P4C1 P8B1 P16A9 P32A29 X0LB12bi /5b P4D0 P8B2 P16A10 X0LB02bi /5b P4D1 P8B3 P16A11 X0LB02bo/5b P4D2 P8B4 P16A12 X0LB12bo/5b P4D3 P8B5 P16A13 X0LB25ob P4C2 P8B6 P16A14 P32A30 X0LB35ob P4C3 P8B7 P16A15 P32A31 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O — — — — — — — — — — — — — — — — — — — — — — RS RS RU RU RU RU RU RU RU RU RS RS RU RU RU RU RU RU RU RU RU RU (continued) Document Number: 1087D 5 Page XS1-G04B-FB144 Datasheet 10 5.6 OTP Each XCore integrates 8 KB one-time programmable (OTP) memory along with a security register that conﬁgures system wide security features. The OTP holds data in 2k rows x 32-bit conﬁguration which can be used to implement secure bootloaders and store encryption keys. Data for the security register is loaded from the OTP on power up. 5.6.1 Security Register The security register enables the following security features: • Secure Boot: The XCore is forced to boot from address 0 of the OTP, allowing the XCore boot ROM to be bypassed (see §5.8). This feature can be used to implement a secure bootloader which loads an encrypted image from external ﬂash, decrypts and CRC checks it with the processor, and discontinues the boot process if the decryption or CRC check fails. XMOS provides a default secure bootloader that can be written to the OTP along with secret decryption keys. • Disable JTAG: The JTAG interface is disabled, making it impossible for the processor state or memory content to be accessed via the JTAG interface. • Disable Link access: Other processors are forbidden access to the processor state via the system switch. Disabling both JTAG and Link access transforms a core into a “secure island” with other cores free for non-secure user application code. • Disable Global Debug access: Disables access to the SS_DEBUG pin. • OTP Master and Sector Lock: Further access to the OTP is prevented by setting the master lock. Locks can also be applied to each of the four OTP sectors individually. These security features provide a strong level of protection and are suﬃcient for providing strong IP security. 5.7 PLL The PLL is used to generate all on-chip clocks. SS_CLK is the reference clock input. It should be supplied with a clock with monotonic rising edges and should be stable before SS_RESET is taken high. Many standard clock frequencies can be used with appropriate settings conﬁgured into the PLL. At boot time, before the PLL can be reconﬁgured, the PLL multiplier is set using the pins speciﬁed in the table in Figure 2. The PLL increases the clock frequency to the core frequency used to run the processor data path and the switch. Document Number: 1087D 11 Page

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