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PDF ISL12082 Data sheet ( Hoja de datos )
| Número de pieza | ISL12082 | |
| Descripción | Real Time Clock | |
| Fabricantes | Intersil | |
| Logotipo |  |
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ISL12082
I2C-Bus Real Time Clock with Two Interrupts, Alarm, and Timer
Data Sheet
September 25, 2015
FN6731.4
Low Power RTC with Battery ReSeal™,
2 IRQs, Hundredths of a Second Time,
and Crystal Compensation
The ISL12082 device is a low power real time clock with
timing and crystal compensation, clock/calendar, power fail
indicator, 2 IRQs, periodic or polled alarm, timer/watchdog,
and intelligent battery backup switching.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, seconds and hundredths of a second. The
device has calendar registers for date, month, year and day
of the week. The calendar is accurate through 2099, with
automatic leap year correction.
Pinouts
ISL12082
(8 LD SOIC)
TOP VIEW
X1
X2
GND
IRQ2
1
2
3
4
8
7
6
5
VDD
IRQ1/fOUT
SCL
SDA
ISL12082
(10 LD MSOP)
TOP VIEW
X1 1
X2 2
VBAT
3
GNNODLONGE4R
AVAILABLE
10
OR9
8
7
SUPPVIRODRQDT1E/fDOUT
SCL
SDA
NC 5
6 IRQ2
Features
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes, Seconds, and
Hundredths of a Second
- Day of the Week, Day, Month, and Year
• 4 Selectable Frequency Outputs
• Alarm
- Settable to the Second, Minute, Hour, Day of the Week,
Day, or Month
- Single Event or Pulse Interrupt Mode
• Timer
- 4 Selectable Timer Functions
- 4 Selectable Timer Clock Frequencies
- Single Event or Pulse Interrupt Mode
• Automatic Backup to Battery or Supercapacitor
• Power Failure Detection
• Battery ReSeal™
• On-Chip Oscillator Compensation
• I2C Interface
- 400kHz Data Transfer Rate
• 800nA Battery Supply Current
• Small Package Options
- 8 Ld SOIC Package
- 10 Ld MSOP Package
• Pb-Free (RoHS Compliant)
Applications
• Utility Meters
• HVAC Equipment
• Audio/Video Components
• Set-Top Box/Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas LLC.
I2C Bus™ is a trademark owned by NXP Semiconductors Netherlands, B.V. Copyright Intersil Americas LLC. 2008, 2015. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL12082
Serial Interface Specifications Over the recommended operating conditions, unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN TYP MAX
(Note 6) (Note 5) (Note 6) UNITS
Cpin
fSCL
tIN
SDA and SCL Pin Capacitance
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
TA = +25°C, f = 1MHz, VDD = 5V, VIN = 0V,
VOUT = 0V
Any pulse narrower than the max spec is
suppressed
10 pF
400 kHz
50 ns
tAA
tBUF
SCL Falling Edge to SDA Output
Data Valid
Time the Bus Must Be Free Before
the Start of a New Transmission
SCL falling edge crossing 30% of VDD, until
SDA exits the 30% to 70% of VDD window
SDA crossing 70% of VDD during a STOP
condition, to SDA crossing 70% of VDD
during the following START condition
1300
900 ns
ns
tLOW
tHIGH
tSU:STA
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
tHD:STA START Condition Hold Time
tSU:DAT Input Data Setup Time
tHD:DAT Input Data Hold Time
Measured at the 30% of VDD crossing
Measured at the 70% of VDD crossing
SCL rising edge to SDA falling edge. Both
crossing 70% of VDD
From SDA falling edge crossing 30% of VDD
to SCL falling edge crossing 70% of VDD
From SDA exiting the 30% to 70% of VDD
window, to SCL rising edge crossing 30% of
VDD
From SCL falling edge crossing 30% of VDD
to SDA entering the 30% to 70% of VDD
window
1300
600
600
600
100
0
ns
ns
ns
ns
ns
900 ns
tSU:STO STOP Condition Setup Time
tHD:STO STOP Condition Hold Time
tDH Output Data Hold Time
From SCL rising edge crossing 70% of VDD,
to SDA rising edge crossing 30% of VDD
From SDA rising edge to SCL falling edge
Both crossing 70% of VDD
From SCL falling edge crossing 30% of VDD,
until SDA enters the 30% to 70% of VDD
window
600
600
0
ns
ns
ns
tR SDA and SCL Rise Time
From 30% to 70% of VDD
20 +
0.1 x Cb
300 ns
tF SDA and SCL Fall Time
From 70% to 30% of VDD
20 +
0.1 x Cb
300 ns
Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip
10 400 pF
Rpu SDA and SCL Bus Pull-Up
Resistor Off-Chip
Maximum is determined by tR and tF
For Cb = 400pF, max is about 2k to ~2.5k
For Cb = 40pF, max is about 15kto ~20k
1
k
NOTES:
2. IRQ and fOUT Inactive.
3. LPMODE = 0 (default).
4. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
5. Typical values are for T = +25°C and 3.3V supply voltage.
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
7. Limits should be considered typical and are not production tested.
8. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate
specification.
9. Parameters are for 10 Ld MSOP package only.
NOTES
7, 8
7, 8
7, 8
7, 8
7, 8
5 FN6731.4
September 25, 2015
5 Page 
ISL12082
3. Alarm (6 bytes): Address 0Ch to 11h.
4. TIMER (4 bytes): Address 12h to 14h, with address 14h
as write-only byte and read back ‘0’..
There are no addresses above 1Fh.
Address 15h to 1Eh are not used. Reads or writes to
addresses 15h to 1Eh will not affect operation of the device
but should be avoided.
Write capability is allowable into the RTC registers (00h to
06h, and 1Fh) only when the WRTC bit (bit 4 of address 07h)
is set to “1”. A multi-byte read or write operation is limited
to one section per operation. Access to another section
requires a new operation. A read or write can begin at any
address within the section.
A register can be read by performing a random read at any
address at any time. This returns the contents of that register
location. Additional registers are read by performing a
sequential read. For the RTC and alarm registers, the read
instruction latches all clock registers into a buffer, so an
update of the clock does not change the time being read. A
sequential read will not result in the output of data from the
memory array. At the end of a read, the master supplies a
stop condition to end the operation and free the bus. After a
read, the address remains at the previous address +1 so the
user can execute a current address read and continue
reading the next register.
TABLE 1. REGISTER MEMORY MAP
REG
BIT
REG
ADDR. SECTION NAME
7
6
5
4
3
2
1
0 RANGE DEFAULT
1Fh RTC
SS
SS23
SS22
SS21
SS20
SS13
SS12
SS11
SS10 0 to 99
00h
00h
SC
0
SC22
SC21
SC20
SC13
SC12
SC11
SC10 0 to 59
00h
01h
MN
OF
MN22
MN21
MN20 MN13
MN12
MN11
MN10 0 to 59
80h
02h
HR MIL
0
HR21
HR20
HR13
HR12
HR11
HR10 0 to 23
00h
03h
DT 0
0
DT21
DT20
DT13
DT12
DT11
DT10 1 to 31
00h
04h
MO 0
0
0
MO20 MO13 MO12 MO11
MO10 1 to 12
00h
05h
YR
YR23
YR22
YR21
YR20
YR13
YR12
YR11
YR10 0 to 99
00h
06h
DW 0
0
0
0
0
DW12 DW11 DW10 0 to 6
00h
07h Status
SR
ARST XSTOP RESEAL WRTC
TMR
ALM
BAT
RTCF
N/A
03h
08h Control INT
IM
ALME LPMODE FOBATB IRQ2E IRQ1E
FO1
FO0 N/A
00h
09h
TMRC
TIM
TMRE TMOD1 TMOD0
0
0 TCLK1 TCLK0 N/A 00h
0Ah
ATR BMATR1 BMATR0 ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
N/A
00h
0Bh
DTR
0
0
DTR5
DTR4
DTR3
DTR2
DTR1
DTR0
N/A
80h
0Ch SCA ESCA ASC22 ASC21 ASC20 ASC13 ASC12 ASC11 ASC10 00 to 59 00h
0Dh MNA EMNA AMN22 AMN21 AMN20 AMN13 AMN12 AMN11 AMN10 00 to 59 00h
0Eh HRA EHRA
Alarm0
0Fh DTA EDTA
0
AHR21 AHR20 AHR13 AHR12 AHR11 AHR10 0 to 23
00h
0
ADT21 ADT20 ADT13 ADT12 ADT11 ADT10 1 to 31
00h
10h
MOA EMOA
0
0
AMO20 AMO13 AMO12 AMO11 AMO10 1 to 12
00h
11h
DWA EDWA
0
0
0
0
ADW12 ADW11 ADW10 0 to 6
00h
12h TDAT TDAT7 TDAT6 TDAT5 TDAT4 TDAT3 TDAT2 TDAT1 TDAT0 0 to 255 00h
13h TIMER TCNT TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 0 to 255 00h
14h
TSDAT
X
TSDAT6 TSDAT5 TSDAT4 TSDAT3 TSDAT2 TSDAT1 TSDAT0 0 to 99
00h
11 FN6731.4
September 25, 2015
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet ISL12082.PDF ] | |
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