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MK1417S 반도체 회로 부품 판매점

S3 Notebook Clock Source



MicroClock 로고
MicroClock
MK1417S 데이터시트, 핀배열, 회로
PRELIMINARY INFORMATION
MK1417
S3 Notebook Clock Source
Description
Features
The MK1417 is an ideal way to generate clocks for
S3’s M5 processor. The chip is a cost reduction to
the MK1416, maintaining the functionality of the
MK1416, but with a different pinout. In an 8 pin
SOIC, the chip saves cost over separate surface
mount oscillators and increases reliability by
eliminating mechanical (quartz-based) devices
from the board. The power down pin turns off the
device, drawing less than 30µA.
MicroClock offers many other clocks for
computers and computer peripherals. Consult
MicroClock when you need to remove crystals and
oscillators from your board.
Block Diagram
• Packaged in 8 pin SOIC
• Functional, lower cost replacement of MK1416
• Differences from MK1416
- no on-chip crystal capacitors
- pinout is different
• Ideal for S3’s M5 processor
• Input clock frequency of 14.31818 MHz
• Dual buffered 14.318 MHz clock outputs
• Output clock frequency of 27.0MHz
• Power down turns off chip
• Low jitter
• 25mA drive capability at TTL levels
• 3.3V or 5V supply voltage
• Advanced, low power CMOS process
• Insensitive to input clock duty cycle
VDD GND
PD
14.31818 MHz
crystal or clock
X1/ICLK
X2
Crystal
Oscillator
PLL
Clock Synthesis
and Control
Circuitry
Output
Buffer
Output
Buffer
Output
Buffer
27.000 MHz
14.31818 MHz
14.31818 MHz
(Capacitors are required for tuning)
MDS1417B
1
Revision 12157
Printed 12/16/97
MicroClock division of ICS•1271 Parkmoor Ave.•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax


MK1417S 데이터시트, 핀배열, 회로
PRELIMINARY INFORMATION
MK1417
S3 Notebook Clock Source
Pin Assignment
X1/ICLK
VDD
GND
14.3M
1
2
3
4
8 X2
7 PD
6 27M
5 14.3M
8 pin SOIC
PD All Clocks
0 LOW
1 ON
Pin Descriptions
Number
1
2
3
4
5
6
7
8
Name
X1/ICLK
VDD
GND
14.3M
14.3M
27M
PD
X2
Type Description
I Crystal Connection. Connnect to a 14.31818 MHz crystal or clock.
P Connect to +3.3V or +5V.
P Connect to ground.
O 14.31818 MHz buffered crystal clock output.
O 14.31818 MHz buffered crystal clock output.
O 27.00 MHz clock output.
I Power Down input. Logic 0 takes all clocks low. Internal pullup.
O Crystal Connection for a 14.31818 MHz crystal, or leave unconnected for clock input.
Key: I = Input, O = output, P = power supply connection
External Components/Crystal Selection
A minimum number of external components are required for proper operation. For a crystal input, a
parallel resonant 14.31818 MHz crystal is recommended. The frequency tolerance of the crystal should be
±30 ppm maximum. For tuning with a given crystal CL, the formula 2•(CL-6) gives the value of each
capacitor that should be connected from X1 to GND and X2 to GND. For a clock input, connect to X1
and leave X2 unconnected. A decoupling capacitor of 0.1µF should be connected between VDD and
GND on pins 2 and 3, and a 33terminating resistor can be used on each clock output if the trace is
longer than 1 inch.
MDS1417B
2
Revision 12157
Printed 12/16/97
MicroClock division of ICS•1271 Parkmoor Ave.•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax




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