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PDF TW5866 Data sheet ( Hoja de datos )
| Número de pieza | TW5866 | |
| Descripción | 9D1 H.264 CODEC | |
| Fabricantes | Intersil | |
| Logotipo |  |
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NOT RECOMMENDED FOR NEW DESIGNS
RECOMMENDED REPLACEMENT PARTS
TW2819, TW2809
9D1 H.264 CODEC with 8-Channel A/V Decoder
TW5866
TW5866 is a H.264 CODEC solution with integrated
8-channel analog A/V decoders. TW5866 supports up to 9D1
of H.264 video encoding, 8D1 of H.264 video decoding, or
4D1 H.264 full duplex codec. In addition, TW5866 supports
motion JPEG encoding and video preview through BT.656
interfaces and PCI interfaces. TW5866 can be used in low
cost H.264 hardware compression PCI card to support either
8-channel with a single chip, or 16-channel with two chips. It
can also work with two external TW2866 to support 16-CIF
H.264 compression. TW5866 can also be used in embedded
DVR applications as an AV front-end chip working with
display mux capable SOCs.
TW5866 integrates 8 A/V decoders. It takes 8 CVBS analog
inputs fed into eight internal high quality NTSC/PAL video
decoders. In addition, it has 2 digital BT.656 / 1120
interfaces, running up to 108/148.5 MHz, capable of
receiving up to 8 D1, 2 720P / 1080i / 1080p HD video
sources. When used as D1 input, the digital interface takes
multi-channel video signal from external video decoders,
such as TW2866 / TW2867. This allows the TW5866 to
support a total of 16 D1 video channels. All the SD / HD
video streams are fed into H.264 encoder, MJPEG encoder
for compression, and to PCI interface and digital 656 output
interface for preview purposes. The H.264 decoded stream
from the on-chip video decoder is fed through two BT.656 /
1120 playback interfaces to drive the external display
processors. The BT.656 playback interfaces runs up to 108
MHz and is capable of delivering multi-channel byte-
interleaving or field/frame interleaving format for total of 8
D1 playback channels.
TW5866 supports functions per channel, such as motion
detection, night detection, and blind detection engine for
channel alarm notification. It features triple scalers per
channel for each of the H.264 encode, MJPEG, and PCI
preview paths. Each of these scalers is independently
configurable. TW5866 also features per channel OSDs and
motion adaptive de-interlacer. TW5866 supports 8-channel
of motion adaptive 2D de-interlacers and 2D noise reduction.
TW5866 integrates a H.264 baseline level 3 compliant
encoder capable of performing up to either 9 D1 equivalent
video encoding (225 fps for PAL and 270 fps for NTSC), 8 D1
decoding, 17 channel G.726 ADPCM hardware audio encoder
with one channel for two way audio communication, and one
channel ADPCM audio decoding. The H.264 video encoder
supports dual-bitstream compression for both local storage
and network streams. It also features a motion JPEG encoder
for up to 25 frames per second shared among all video
channels.
TW5866 provides PCI interface for external CPU control and
bitstream upload. The PCI interface runs at 33 or 66 MHz The
external CPU can access the internal meta-data associated
with each H.264 channel for video analytic purposes.
Analog Video Decoder
8 CVBS analog inputs fed into 8 sets of video decoder
accept all NTSC(M/N/4.43) / PAL
(B/D/G/H/I/K/L/M/N/60) standards with auto detection
Integrated video analog anti-aliasing filters and 10-bit
CMOS ADCs for each video decoder
High performance adaptive 4H comb filters for all
NTSC/PAL standards
IF compensation filter for improvement of color
demodulation
Color Transient Improvement (CTI)
Automatic white peak control
Programmable hue, saturation, contrast, brightness and
sharpness
Proprietary fast video locking system for non-real-time
application
Noise Reduction to remove impulse noise
Digital Input Ports
BT.656
Two BT.656 ports at up to 108 MHz interfaced with 2
external TW2866s
Byte-interleaving supports 4 channels multiplexing with
each channel of interlaced D1 at 60/50 fps
BT.1120
Two BT.1120 ports to support external HD video sources
of 720P / 1080i / 1080p format at 74.25 / 148.5 MHz
One cascade input supporting cascade of multiple
TW5866 chips. This is pin shared with one playback port
Pre-processing
Per channel triple high performance down scalers of each
channel scale independently for H.264, JPEG and preview
output
Per channel motion detector with 16 X 12 cells
Per channel night / blind detections
Per channel noise reduction and de-interlacing to convert
Interlaced video into progressive before compression
Per channel OSD for information overlay
Single Box
1-bit per pixel text
2-bit per pixel text or mask
12-bit per pixel bitmap
FN8319.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
February 27, 2013
All other trademarks mentioned are the property of their respective owners.
1 page  
TW5866
Table of Contents
Analog Video Decoder ......................................................... 1
Digital Input Ports ................................................................ 1
Pre-processing ...................................................................... 1
Digital Preview Ports............................................................ 2
Digital Playback Ports ......................................................... 2
H.264 Video Encoder ........................................................... 2
H.264 Video Decoder........................................................... 2
Video Analytic Interface ...................................................... 2
Motion JPEG Encoder........................................................... 2
Analog Audio CODEC ........................................................... 2
Digital Audio CODEC ............................................................ 2
DDR2 Interface..................................................................... 2
Host Interface ....................................................................... 2
System Clock ........................................................................ 2
Package ................................................................................. 2
Ordering Information...................................................................... 3
Application ....................................................................................... 4
Table of Contents............................................................................ 5
Table of Figures............................................................................... 6
Table List .......................................................................................... 7
Pin Configuration (416 BGA)......................................................... 8
Ball Descriptions ............................................................................. 9
Analog Interface ................................................................... 9
PCI Interface .......................................................................10
Misc Host Interface ............................................................11
Digital Video Interface .......................................................12
Digital Audio Interface.......................................................13
DDR2 SDRAM Interface ....................................................14
Misc Control Interfaces......................................................15
Power / Ground ..................................................................16
Unconnected .......................................................................17
Functional Description .................................................................18
CVBS Video Input................................................................18
Formats.................................................................................................18
Analog Front-End...............................................................................19
Decimation Filter...............................................................................19
AGC and Clamping...........................................................................20
Sync Processing.................................................................................20
Y/C Separation...................................................................................20
Color Decoding...................................................................................20
ACC (Automatic Color gain control)............................................22
Chrominance Processing...............................................................22
ITU-R BT. 656 Digital Input ...............................................24
ITU-R BT. 1120 Video Input...............................................28
ITU-R BT. 656 Preview Video Output ...............................28
ITU-R BT. 656 SD Playback Output..................................28
Byte-Interleaved Format.................................................................29
Frame/Field-Interleaved Format.................................................29
ITU-R BT. 1120 HD Playback Output ...............................30
TW5866 Cascade through BT. 1120...............................30
Pre-processing Module ......................................................31
Downscalers ........................................................................32
Motion Detection ................................................................32
Mask and Detection Region Selection............................32
Sensitivity Control...............................................................32
Level Sensitivity ..................................................................32
Spatial Sensitivity...............................................................32
Temporal Sensitivity ..........................................................32
Velocity Control...................................................................32
Blind Detection ...................................................................35
Night Detection...................................................................35
H.264 Encoding Channel Capture ...................................36
MJPEG Encoding Channel Capture ..................................37
PCI Preview Channel Selection ........................................38
H.264 Encoding Module....................................................40
De-Interlacers......................................................................................40
5
OSDs 40
H.264 Encoders.................................................................................40
H.264 Coded Stream......................................................................40
Audio A/D and D/A CODEC .............................................. 42
Serial Audio Interface........................................................ 44
Playback Input.................................................................... 44
Record Output .................................................................... 44
Mix Output........................................................................... 46
Audio Multi-Chip Cascade................................................. 46
Audio Clock Generation .................................................... 47
Audio master clock per field.........................................................47
Audio master clock nominal increment...................................47
Audio Clock Auto Setup .................................................... 49
Digital Audio Encoding / Decoding ................................. 49
Host Interfaces ................................................................... 50
PCI Interface ....................................................................... 50
Single Read / Write..........................................................................50
Target Burst Read / Write..............................................................50
Master Burst Write...........................................................................50
Asynchronous Interface .................................................... 50
External DRAM Interface .................................................. 50
Register Descriptions................................................................... 52
0x0000 ~ 0x3FFF: H.264 Codec Control........................ 52
VLCE Registers...................................................................................64
VLCD Registers..................................................................................68
0x4000 ~ 0x4074: Audio ADPCM................................... 71
0x8100 ~ 0x813C: VD_VP_VJ_HD ................................. 76
0x8200 ~ 0x849C: Senif_HD........................................... 79
0x8800 ~ 0x883C: Interrupt ............................................ 82
0x9000 ~ 0x920C: Video Capture (VIF).......................... 85
0x9800: GPIO ..................................................................... 88
0xA000 ~ 0xA098: DDR2 Control................................... 89
0xA800 ~ 0xABFC: Playback Control ............................. 97
0xB000 ~ 0xB028: Debug Control................................111
0xC800 ~ 0xC804 -- JPEG Capture Register Map.......112
0xD000 ~ 0xD0FC: MJPEG Control ..............................113
0xD800 ~ 0xD93C: DDR mapping/EMUIF..................121
0xE000 ~ 0xFC00: Motion Vector .................................129
0x18000 ~ 0x181FC: PCI Master..................................130
0x180A0 – 0x180BC: Audio Burst Base Address.......138
0x180C0 – 0x180DC: JPEG Burst Base Address........138
0x180E0: Grab Buffer Base Address ............................138
0x180F0 – 0x180FC: HD Preview Base Address........138
0x18100 – 0x1817C: Preview Base Address .............139
0x18180 – 0x181BC: VLC MV Flag Base Address .....140
0x181C0 – 0x181FC: PREV MV Flag Base Address...140
0x1C000 ~ 0x1CFFF: Analog Front-end .......................141
0x1D400 ~ 0x1D7FF: SD Scalers/Interrupts ..............185
0x1D800 ~ 0x1DBFF: SD MD/BD/ND..........................187
0x1DC00 ~ 0x1DFFF: HD MD/BD/ND..........................196
0x1F400 ~ 0x1F7FF: DDR2 PHY Control .....................205
0x1F800 ~ 0x1FBFF: MISC & PLL / Analog IP............212
Parametric Information.............................................................220
Absolute Maximum Ratings ...........................................220
Thermal Information .......................................................220
AC/DC Electrical Parameters.........................................220
Video Decoder AC/DC Specifications ...........................222
DDR2 Interface Electrical Characteristics....................223
DDR2 Interface AC Timing .............................................224
PCI Interface AC Timing ..................................................226
Video Inputs AC Timing ...................................................227
Video Outputs AC Timing ................................................227
I2C Interface AC Timing ...................................................229
Package Outline Drawing..........................................................230
Revision History...........................................................................231
5 Page 
Misc Host Interface
TW5866
NAME
GPIO[7:0]
MODE_SEL
BALL #
(MSB FIRST FOR BUS
SIGNALS)
AE25, AF25, AE24,
AF24, AD23, AE23,
AF23, AD22
AE22
I2C_SDA
AF26
I2C_SCL
ASYNC_ADDR[17:0]
ASYNC_CS
AE26
AC21, AD21, AE21,
AF21, AC20, AD20,
AE20, AF20, AC19,
AD19, AE19, AF19,
AC18, AD18, AE18,
AF18, AC17, AD17
AF22
TYPE
DESCRIPTION
I/O General Purpose IO
I
PCI Mode Select.
1: PCI, 0: Asynchronous Host Interface
I/O
I2C Data Signal. The I2C signal is master, and used to control the
external TW286x video decoder chips only.
I/O
I2C Clock Signal. The I2C signal is master, and used to control the
external TW286x video decoder chips only.
O Asynchronous Host Interface Address Bus
O Asynchronous Host Interface chip select signal
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TW5866.PDF ] | |
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