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IDT70V9359 반도체 회로 부품 판매점

HIGH-SPEED 3.3V 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM



IDT 로고
IDT
IDT70V9359 데이터시트, 핀배열, 회로
HIGH-SPEED 3.3V 8/4K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
IDT70V9359/49L
Features:
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 6.5/7.5/9ns (max.)
– Industrial: 7.5ns (max.)
Low-power operation
– IDT70V9359/49L
Active: 450mW (typ.)
Standby: 1.5mW (typ.)
Flow-Through or Pipelined output mode on either port via
the FT/PIPE pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Functional Block Diagram
Full synchronous operation on both ports
– 3.5ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time, 100MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (–40°C to +85°C) is
available for 83 MHz
Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-
pin Fine Pitch Ball Grid Array (fpBGA) packages.
R/WL
UBL
CE0L
CE1L
LBL
OEL
1
0
0/1
FT/PIPEL
I/O9L-I/O17L
I/O0L-I/O8L
A12L(1)
A0L
CLKL
ADSL
CNTENL
CNTRSTL
0/1 1b 0b b a 1a 0a
Counter/
Address
Reg.
I/O
Control
I/O
Control
MEMORY
ARRAY
1
0
0/1
0a 1a a b0b 1b 0/1
Counter/
Address
Reg.
NOTE:
1. A12 is a NC for IDT70V9349.
R/WR
UBR
CE0R
CE1R
LBR
OER
FT/PIPER
I/O9R-I/O17R
I/O0R-I/O8R
A12R(1)
A0R
CLKR
ADSR
CNTENR
CNTRSTR
5638 drw 01
©2003 Integrated Device Technology, Inc.
1
AUGUST 2003
DSC-5638/3


IDT70V9359 데이터시트, 핀배열, 회로
IDT70V9359/49L
High-Speed 3.3V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70V9359/49 is a high-speed 8/4K x 18 bit synchronous
Dual-Port RAM. The memory array utilizes Dual-Port memory cells
to allow simultaneous access of any address from both ports.
Registers on control, data, and address inputs provide minimal setup
and hold times. The timing latitude provided by this approach allows
systems to be designed with very short cycle times.
With an input data register, the IDT70V9359/49 has been optimized for
applications having unidirectional or bidirectional data flow in bursts. An
automatic power down feature, controlled by CE0 and CE1, permits the
on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 450mW of power.
Pin Configurations(1,2,3,4)
07/03/02
Index
A9L
A10L
A11L
A12L(1)
NC
NC
NC
LBL
UBL
CE0L
CE1L
CNTRSTL
R/WL
OEL
VDD
FT/PIPEL
I/O17L
I/O16L
VSS
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
1 100
99 98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
2 74
3 73
4 72
5 71
6 70
7 69
8 68
9 67
10
70V9359/49PF
66
11
PN100-1(5)
65
12
100-Pin TQFP
64
13
Top View(6)
63
14 62
15 61
16 60
17 59
18 58
19 57
20 56
21 55
22 54
23 53
24 52
25 51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A8R
A9R
A10R
A11R
A12R(1)
NC
NC
NC
LBR
UBR
CE0R
CE1R
CNTRSTR
R/WR
VSS
OER
FT/PIPER
I/O17R
VSS
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
.
5638 drw 02
NOTES:
1. A12 is a NC for IDT70V9349.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.422




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IDT70V9359

HIGH-SPEED 3.3V 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM - IDT



IDT70V9359L

HIGH-SPEED 3.3V 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM - IDT