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PDF IDT70V9369L Data sheet ( Hoja de datos )
| Número de pieza | IDT70V9369L | |
| Descripción | HIGH-SPEED 3.3V 16K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM | |
| Fabricantes | IDT | |
| Logotipo |  |
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HIGH-SPEED 3.3V 16K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
IDT70V9369L
Features:
◆ True Dual-Ported memory cells which allow simultaneous
access of the same memory location
◆ High-speed clock to data access
– Commercial: 6/7.5/9/12ns (max.)
– Industrial: 7.5ns (max.)
◆ Low-power operation
– IDT70V9369L
Active: 500mW (typ.)
Standby: 1.5mW (typ.)
◆ Flow-Through or Pipelined output mode on either port via
the FT/PIPE pins
◆ Counter enable and reset features
◆ Dual chip enables allow for depth expansion without
additional logic
◆ Full synchronous operation on both ports
– 4ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 12ns cycle time, 83MHz operation in Pipelined output mode
◆ Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
◆ LVTTL- compatible, single 3.3V (±0.3V) power supply
◆ Industrial temperature range (–40°C to +85°C) is
available for selected speeds
◆ Available in a 100-pin Thin Quad Flatpack (TQFP)
◆ Green parts available, see ordering information
Functional Block Diagram
R/WL
UBL
CE0L
CE1L
LBL
OEL
1
0
0/1
FT/PIPEL
I/O9L-I/O17L
I/O0L-I/O8L
A13L
A0L
CLKL
ADSL
CNTENL
CNTRSTL
0/1
1b 0b
b
a 1a 0a
Counter/
Address
Reg.
I/O
Control
I/O
Control
MEMORY
ARRAY
1
0
0/1
0a 1a
a
b0b 1b
0/1
Counter/
Address
Reg.
R/WR
UBR
CE0R
CE1R
LBR
OER
FT/PIPER
I/O9R-I/O17R
I/O0R-I/O8R
A13R
A0R
CLKR
ADSR
CNTENR
CNTRSTR
5648 drw 01
©2015 Integrated Device Technology, Inc.
1
JUNE 2015
DSC-5648/5
1 page  
IDT70V9369L
High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V)
70V9369L
Symbol
Parameter
|ILI| Input Leakage Current(1)
Test Conditions
VDD = 3.6V, VIN = 0V to VDD
Min. Max. Unit
___ 5 µA
|ILO| Output Leakage Current
VOL Output Low Voltage
VOH Output High Voltage
NOTE:
1. AtVDD< 2.0Vinputleakagesareundefined.
CEO = VIH or CE1 = VIL, VOUT = 0V to VDD
IOL = +4mA
IOH = -4mA
___ 5 µA
___ 0.4 V
2.4 ___ V
5648 tbl 08
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range(3) (VDD = 3.3V ± 0.3V)
70V9369L6
Com'l Only
70V9369L7
Com'l
& Ind
70V9369L9
Com'l Only
70V9369L12
Com'l Only
Symbol
Parameter
Test Condition
Version
Typ.(4) Max. Typ.(4) Max. Typ.(4) Max. Typ.(4) Max. Unit
IDD Dynamic Operating CEL and CER= VIL,
Current (Both
Outputs Disabled,
Ports Active)
f = fMAX(1)
COM'L L 220 350 200 290 180 225 150 205 mA
IND L ____ ____ 200 335 ____ ____ ____ ____
ISB1 Standby Current CEL = CER = VIH
(Both Ports - TTL
Level Inputs)
f = fMAX(1)
COM'L L 70 130 65 100 50 65 40 50 mA
IND L ____ ____ 65 115 ____ ____ ____ ____
ISB2 Standby
Current (One
Port - TTL
Level Inputs)
CE"A" = VIL and
CE"B" = VIH(5)
Active Port Outputs
Disabled, f=fMAX(1)
COM'L L 150 250 140 210 110 150 100 140 mA
IND L ____ ____ 140 240 ____ ____ ____ ____
ISB3 Full Standby
Current (Both
Ports - CMOS
Level Inputs)
Both Ports CEL and
CER > VDD - 0.2V,
VIN > VDD - 0.2V or
VIN < 0.2V, f = 0(2)
COM'L L 0.4 5 0.4 5 0.4 5 0.4 5 mA
IND L ____ ____ 0.4 15 ____ ____ ____ ____
ISB4 Full Standby
Current (One
Port - CMOS
Level Inputs)
CE"A" < 0.2V and
COM'L L 140
240
130 200
100 140
90
130 mA
CE"B" > VDD - 0.2V(5)
VIN > VDD - 0.2V or
IND L
VIN < 0.2V, Active Port,
130 230____ ____
____ ____ ____ ____
Outputs Disabled, f = fMAX(1)
5648 tbl 09
NOTES:
1. Atf=fMAX,addressandcontrollines(exceptOutputEnable)arecyclingatthemaximumfrequencyclockcycleof1/tCYC,using"ACTESTCONDITIONS"atinputlevelsofGNDto3V.
2. f=0meansnoaddress,clock,orcontrollineschange.AppliesonlytoinputatCMOSlevelstandby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDDDC(f=0)= 90mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V
CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6.452
5 Page 
IDT70V9369L
High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2
tCH2
tCL2
CLK
CE0
CE1
UB, LB
R/W
ADDRESS(4)
DATAIN
DATAOUT
tSC tHC
tSB tHB
tSW tHW
An
tSA tHA
An +1
tCD2
(2)
READ
tSW tHW
An + 2
An + 2
tSD tHD
An + 3
Dn + 2
tCKHZ(1)
Qn
NOP(5)
WRITE
An + 4
tCKLZ(1)
tCD2
Qn + 3
READ
5648 drw 11 .
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
tCYC2
tCH2
tCL2
CLK
CE0
CE1
UB, LB
R/W
tSC tHC
tSB tHB
tSW tHW
tSW tHW
(4)
ADDRESS
DATAIN
DATAOUT
An
tSA tHA
(2)
An +1
An + 2
tSD tHD
Dn + 2
tCD2
Qn
tOHZ(1)
An + 3
Dn + 3
An + 4
An + 5
tCKLZ(1)
tCD2
Qn + 4
OE
READ
WRITE
READ
NOTES:
1. Transitionismeasured0mVfromLoworHigh-impedancevoltagewith theOutputTestLoad(Figure2).
2. Outputstate(High,Low,orHigh-impedance)isdeterminedbythepreviouscyclecontrolsignals.
3. CE0, UB, LB, and ADS = VIL; CE1 and CNTRST = VIH. "NOP" is "No Operation".
4. Addressesdonothavetobeaccessedsequentiallysince ADS=VIL constantlyloadstheaddressontherisingedgeoftheCLK;numbersarefor
reference use only.
5. "NOP"is"NoOperation."Datainmemoryattheselectedaddressmaybecorruptedandshouldbere-writtentoguaranteedataintegrity.
.
5648 drw 12
6.4121
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