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AD7176-2 반도체 회로 부품 판매점

Sigma-Delta ADC



Analog Devices 로고
Analog Devices
AD7176-2 데이터시트, 핀배열, 회로
Data Sheet
24-Bit, 250 kSPS Sigma-Delta ADC
with 20 µs Settling
AD7176-2
FEATURES
Fast and flexible output rate—5 SPS to 250 kSPS
Fast settling time—20 µs
Channel scan data rate of 50 kSPS/channel
Performance specifications
17 noise free bits at 250 kSPS
20 noise free bits at 2.5 kSPS
22 noise free bits at 5 SPS
INL ±2.5 ppm of FSR
85 dB rejection of 50 Hz and 60 Hz with 50 ms settling
User-configurable input channels
2 fully differential or 4 pseudo differential
Crosspoint multiplexer
On-chip 2.5 V reference (drift 2 ppm/°C)
Internal oscillator, external crystal, or external clock
Power supply
Single supply: 5 V AVDD1, 2 V to 5 V AVDD2 and IOVDD
Optional split supply: AVDD1 and AVSS ± 2.5 V
Current: 7.8 mA
Temperature range: −40°C to +105°C
3- or 4-wire serial digital interface (Schmitt trigger on SCLK)
CRC error checking
SPI, QSPI, MICROWIRE, and DSP compatible
APPLICATIONS
Process control: PLC/DCS modules
Temperature and pressure measurement
Medical and scientific multichannel instrumentation
Chromatography
GENERAL DESCRIPTION
The AD7176-2 is a fast settling, highly accurate, high resolution,
multiplexed Σ-Δ analog-to-digital converter (ADC) for low band-
width input signals. Its inputs can be configured as two fully
differential or four pseudo differential inputs via the integrated
crosspoint multiplexer. An integrated precision, 2.5 V, low drift
(2 ppm/°C), band gap internal reference (with an output
reference buffer) adds functionality and reduces the external
component count.
The maximum channel scan data rate is 50 kSPS/channel
(settling time of 20 µs), resulting in fully settled data with
17 noise free bits. User-selectable output data rates range from
5 SPS to 250 kSPS. The resolution increases at lower speeds.
The AD7176-2 offers three key digital filters. The fast settling
sinc5 + sinc1 filter maximizes the channel scan rate. The sinc3
filter maximizes the resolution for single-channel, low speed
applications. For 50 Hz and 60 Hz environments, the AD7176-2
specific filter minimizes the settling times or maximizes the
rejection of the line frequency. These enhanced filters enable
simultaneous 50 Hz and 60 Hz rejection with a 27 SPS output
data rate (with a settling time of 36 ms).
System offset and gain errors can be corrected on a per channel
basis. This per channel configurability extends to the output data
rate used for each channel when using a sinc5 + sinc1 filter. All
switching of the crosspoint multiplexer is controlled by the ADC
and can be configured to automatically control an external
multiplexer via the GPIO pins.
The specified operating temperature range is −40°C to +105°C.
The AD7176-2 is housed in a 24-lead TSSOP package.
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 REGCAPA REF– REF+ REFOUT
IOVDD REGCAPD
1.8V
LDO
BUFFERED
PRECISION
REFERENCE
1.8V
LDO
AIN0
AIN1
AIN2
AIN3
AIN4
INT
REF
Σ-Δ ADC
DIGITAL
FILTER
SERIAL
INTERFACE
AND CONTROL
GPIO AND
MUX
I/O CONTROL
CROSSPOINT
MULTIPLEXER
XTAL AND INTERNAL
CLOCK OSCILLATOR
CIRCUITRY
AVSS
GPIO0 GPIO1
XTAL1 CLKIO/XTAL2
Figure 1.
AD7176-2
DGND
CS
SCLK
DIN
DOUT/RDY
SYNC/ERROR
Rev. D
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com


AD7176-2 데이터시트, 핀배열, 회로
AD7176-2* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
View a parametric search of comparable parts
Evaluation Kits
• AD7176-2 Evaluation Board
Documentation
Data Sheet
AD7176-2: 24-Bit, 250 kSPS Sigma-Delta ADC with 20 μs
Settling Data Sheet
Technical Books
• The Data Conversion Handbook, 2005
User Guides
• UG-478: Evaluation Board for the AD7176-2—24-Bit, 250
kSPS Sigma-Delta ADC with 20 μs Settling
Software and Systems Requirements
• AD7176-2 FMC-SDP Interposer & Evaluation Board /
Xilinx KC705 Reference Design
• AD717x Microcontroller No-OS
• BeMicro FPGA Project for AD7176-2 with Nios driver
• AD717x Eval+ Software
Tools and Simulations
• AD7176-2 Digital Filter Frequency Response Model
• AD7176-2 IBIS Model
Reference Designs
• CN0292
• CN0310
• CN0364
Reference Materials
Press
• Analog Devices’ 24-bit Sigma-Delta A/D Converter
Achieves Twice the Speed of Competing Converters and
Industry’s Best Noise Performance
Technical Articles
• Flexible Bandwidth 4 mA to 20 mA Current Input with
Easy HART Compatibility
Tutorials
• MT-022: ADC Architectures III: Sigma-Delta ADC Basics
• MT-023: ADC Architectures IV: Sigma-Delta ADC
Advanced Concepts and Applications
Design Resources
• AD7176-2 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
View all AD7176-2 EngineerZone Discussions
Sample and Buy
Visit the product page to see pricing options
Technical Support
Submit a technical question or find your regional support
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* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
frequently modified.




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