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ADF4110 반도체 회로 부품 판매점

RF PLL Frequency Synthesizers



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Analog Devices
ADF4110 데이터시트, 핀배열, 회로
Data Sheet
RF PLL Frequency Synthesizers
ADF4110/ADF4111/ADF4112/ADF4113
FEATURES
GENERAL DESCRIPTION
ADF4110: 550 MHz; ADF4111: 1.2 GHz; ADF4112: 3.0 GHz;
ADF4113: 4.0 GHz
2.7 V to 5.5 V power supply
Separate charge pump supply (VP) allows extended tuning
voltage in 3 V systems
Programmable dual-modulus prescaler 8/9, 16/17, 32/33,
64/65
The ADF4110 family of frequency synthesizers can be used to
implement local oscillators in the upconversion and downcon-
version sections of wireless receivers and transmitters. They
consist of a low noise digital PFD (phase frequency detector), a
precision charge pump, a programmable reference divider,
programmable A and B counters, and a dual-modulus prescaler
Programmable charge pump currents
(P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction
Programmable antibacklash pulse width
with the dual-modulus prescaler (P/P + 1), implement an N
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
divider (N = BP + A). In addition, the 14-bit reference counter
(R counter) allows selectable REFIN frequencies at the PFD
input. A complete phase-locked loop (PLL) can be implemented
APPLICATIONS
Base stations for wireless radio (GSM, PCS, DCS, CDMA,
if the synthesizer is used with an external loop filter and voltage
controlled oscillator (VCO).
WCDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANS
Communications test equipment
Control of all the on-chip registers is via a simple 3-wire
interface. The devices operate with a power supply ranging
from 2.7 V to 5.5 V and can be powered down when not in use.
CATV equipment
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
VP CPGND
RSET
REFERENCE
REFIN
CLK
DATA
LE
RFINA
RFINB
24-BIT
INPUT REGISTER 22
SDOUT
14-BIT
R COUNTER
14
R COUNTER
LATCH
FUNCTION
LATCH
A, B COUNTER
LATCH
19
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
LOCK
DETECT
CURRENT CURRENT
SETTING 1 SETTING 2
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
FROM
FUNCTION
LATCH
13
N = BP + A
13-BIT
B COUNTER
PRESCALER
P/P +1
LOAD
LOAD
6-BIT
A COUNTER
AVDD
SDOUT
MUX
HIGH Z
M3 M2 M1
ADF4110/ADF4111
6 ADF4112/ADF4113
CE
AGND
DGND
Figure 1. Functional Block Diagram
CP
MUXOUT
Rev. F
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Tel: 781.329.4700
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Technical Support
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ADF4110 데이터시트, 핀배열, 회로
ADF4110/ADF4111/ADF4112/ADF4113
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics..................................................................... 5
Absolute Maximum Ratings............................................................ 6
Transistor Count........................................................................... 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Circuit Description......................................................................... 12
Reference Input Section............................................................. 12
RF Input Stage............................................................................. 12
Prescaler (P/P + 1)...................................................................... 12
A and B Counters ....................................................................... 12
R Counter .................................................................................... 12
Data Sheet
Phase Frequency Detector (PFD) and Charge Pump............ 13
Muxout and Lock Detect........................................................... 13
Input Shift Register .................................................................... 13
Function Latch............................................................................ 19
Initialization Latch ..................................................................... 20
Device Programming after Initial Power-Up ......................... 20
Resynchronizing the Prescaler Output.................................... 21
Applications..................................................................................... 22
Local Oscillator for GSM Base Station Transmitter .............. 22
Using a D/A Converter to Drive the RSET Pin......................... 23
Shutdown Circuit ....................................................................... 23
Wideband PLL ............................................................................ 23
Direct Conversion Modulator .................................................. 25
Interfacing ................................................................................... 26
PCB Design Guidelines for Chip Scale Package .................... 26
Outline Dimensions ....................................................................... 27
Ordering Guide............................................................................... 28
REVISION HISTORY
1/13—Rev. E to Rev. F
Changes to Table 1.............................................................................4
Changes to Ordering Guide ...........................................................28
8/12—Rev. D to Rev. E
Changed CP-20-1 to CP-20-6 ........................................... Universal
Updated Outline Dimensions ........................................................28
Changes to Ordering Guide ...........................................................28
5/12—Rev. C to Rev. D
Changes to Figure 2...........................................................................5
Changes to Figure 4 and Table 4......................................................7
Updated Outline Dimensions ........................................................28
Changes to Ordering Guide ...........................................................28
3/04—Data sheet changed from Rev. B to Rev. C.
Updated Format.................................................................. Universal
Changes to Specifications .................................................................2
Changes to Figure 32.......................................................................22
Changes to the Ordering Guide.....................................................28
3/03—Data sheet changed from Rev. A to Rev. B.
Edits to Specifications .......................................................................2
Updated OUTLINE DIMENSIONS .............................................24
1/01—Data sheet changed from Rev. 0 to Rev. A.
Changes to DC Specifications in B Version, B Chips,
Unit, and Test Conditions/Comments Columns .....................2
Changes to Absolute Maximum Rating .........................................4
Changes to FRINA Function Test .....................................................5
Changes to Figure 8...........................................................................7
New Graph Added—TPC 22 ...........................................................9
Change to PD Polarity Box in Table V .........................................15
Change to PD Polarity Box in Table VI........................................16
Change to PD Polarity Paragraph .................................................17
Addition of New Material
(PCB Design Guidelines for Chip–Scale package) ................23
Replacement of CP-20 Outline with CP-20 [2] Outline ............24
Rev. F | Page 2 of 28




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