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PDF 9ZXL1550 Data sheet ( Hoja de datos )
| Número de pieza | 9ZXL1550 | |
| Descripción | 15-output DB1900Z Low-Power Derivative | |
| Fabricantes | IDT | |
| Logotipo |  |
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15-output DB1900Z Low-Power Derivative
9ZXL1550
DATASHEET
Description
The 9ZXL1550 is a DB1900Z derivative buffer utilizing
Low-Power HCSL (LP-HCSL) outputs to increase edge rates
on long traces, reduce board space, and reduce power
consumption more than 50% from the original 9ZX21501. It is
pin-compatible to the 9ZXL1530 and has the output
terminations integrated. It is suitable for PCI-Express
Gen1/2/3 or QPI/UPI applications, and uses a fixed external
feedback to maintain low drift for demanding QPI/UPI
applications.
Recommended Application
Buffer for Romley, Grantley and Purley Servers
Key Specifications
• Cycle-to-cycle jitter: < 50ps
• Output-to-output skew: <75ps
• Input-to-output delay variation: <50ps
• Phase jitter: PCIe Gen3 < 1ps rms
• Phase jitter: QPI 9.6GB/s < 0.2ps rms
Block Diagram
Features/Benefits
• LP-HCSL outputs; up to 90% IO power reduction, better
signal integrity over long traces
• Direct connect to 85Ω transmission lines; eliminates 60
termination resistors, saves 103mm2 area
• Pin compatible to the 9ZXL1530; easy upgrade to reduced
board space
• 64-VFQFPN package; smallest 15 output Z-buffer
• Fixed feedback path: ~ 0ps input-to-output delay
• 9 Selectable SMBus addresses; multiple devices can share
same SMBus segment
• Separate VDDIO for outputs; allows maximum power
savings
• PLL or bypass mode; PLL can dejitter incoming clock
• 100MHz & 133.33MHz PLL mode; legacy QPI/UPI support
• Selectable PLL BW; minimizes jitter peaking in downstream
PLL's
• Spread spectrum compatible; tracks spreading input clock
for EMI reduction
• SMBus Interface; unused outputs can be disabled
Output Features
• 15 - LP-HCSL Differential Output Pairs w/integrated
terminations (Zo = 85)
DIF_IN
DIF_IN#
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Logic
Z-PLL
(SS Compatible)
9ZXL1550 REVISION E 11/20/15
1
FBOUT_NC
DIF(14:0)
©2015 Integrated Device Technology, Inc.
1 page  
9ZXL1550 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9ZXL1550. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
3.3V Core Supply Voltage VDDA, R
3.3V Logic Supply Voltage VDD
I/O Supply Voltage
VDDIO
Input Low Voltage
VIL
Input High Voltage
VIH
Except for SMBus interface
Input High Voltage
VIHSMB
SMBus clock and data pins
Storage Temperature
Ts
Junction Temperature
Tj
Input ESD protection
ESD prot
Human Body Model
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
MIN
GND-0.5
-65
2000
TYP
UNITS NOTES
MAX
4.6 V 1,2
4.6 V 1,2
4.6 V 1,2
V1
VDD+0.5V
5.5V
V
V
1
1
150 °C 1
125 °C 1
V1
Electrical Characteristics–DIF_IN Clock Input Parameters
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Input Crossover Voltage -
DIF_IN
VCROSS
Cross Over Voltage
150 900 mV 1
Input Swing - DIF_IN
VSWING
Differential value
300
mV 1
Input Slew Rate - DIF_IN dv/dt
Measured differentially
0.4
8 V/ns 1,2
Input Leakage Current
Input Duty Cycle
IIN
dtin
VIN = VDD , VIN = GND
Measurement from differential wavefrom
-5
45
5 uA
55 % 1
Input Jitter - Cycle to Cycle JDIFIn
Differential Measurement
1 Guaranteed by design and characterization, not 100% tested in production.
2Slew rate measured through +/-75mV window centered around differential zero
0
125 ps 1
REVISION E 11/20/15
5 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE
5 Page 
9ZXL1550 DATASHEET
General SMBus Serial Interface Information
How to Write
• Controller (host) sends a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the byte count = X
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through Byte
N+X-1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
Index Block Write Operation
Controller (Host)
IDT (Slave/Receiver)
T starT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
O
OO
OO
O
Byte N + X - 1
ACK
P stoP bit
How to Read
• Controller (host) will send a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) will send a separate start bit
• Controller (host) sends the read address
• IDT clock will acknowledge
• IDT clock will send the data byte count = X
• IDT clock sends Byte N+X-1
• IDT clock sends Byte 0 through Byte X (if X(H) was
written to Byte 8)
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Controller (Host)
IDT (Slave/Receiver)
T starT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address
RD ReaD
ACK
ACK
ACK
O
O
O
N Not acknowledge
P stoP bit
Data Byte Count=X
Beginning Byte N
O
O
O
Byte N + X - 1
REVISION E 11/20/15
11 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet 9ZXL1550.PDF ] | |
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