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IDT |
12-output DB1200ZL Derivative with
Integrated 85Ω Terminations
9ZXL1251
DATASHEET
General Description
The 9ZXL1251 meets the demanding requirements of the
Intel DB1200ZL specification, including the critical low-drift
requirements of Intel CPUs. It is pin compatible to the
9ZXL1231 and integrates 24 termination resistors, saving
41mm2 board area.
Recommended Application
Buffer for Romley, Grantley and Purley Servers, solid state
storage and PCIe
Output Features
• 12 LP-HCSL Output Pairs w/integrated terminations (Zo =
85Ω)
Key Specifications
• Cycle-to-cycle jitter <50ps
• Output-to-output skew <50ps
• Input-to-output delay variation <50ps
• PCIe Gen3 phase jitter <1.0ps RMS
• Phase jitter: QPI/UPI >=9.6GB/s <0.2ps rms
Features/Benefits
• 85Ω Low-power push-pull HCSL outputs; eliminate 24
resistors, save 41mm2 of area
• Pin compatible to 9ZX21201 and 9ZXL1231; easy path to
power and area savings
• Space-saving 64-pin VFQFPN package
• Fixed feedback path for 0ps input-to-output delay
• 9 Selectable SMBus Addresses; multiple devices can
share the same SMBus Segment
• 12 OE# pins; hardware control of each output
• PLL or bypass mode; supports common and separate clock
architectures
• Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLL's
• Spread Spectrum Compatible; tracks spreading input clock
for low EMI
• -40°C to +85°C device available; supports demanding
environmental applications
Block Diagram
OE(11:0)#
DIF_IN
DIF_IN#
Z-PLL
(SS Compatible)
DFB_OUT_NC
DIF(11:0)
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Logic
9ZXL1251 REVISION B 11/20/15 1 ©2015 Integrated Device Technology, Inc.
9ZXL1251 DATASHEET
Pin Configuration
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VDDA 1
48 GND
GNDA 2
47 DIF_7#
NC 3
46 DIF_7
^100M_133M# 4
^vHIBW_BYPM_LOBW# 5
45 vOE7#
44 vOE6#
CKPWRGD_PD# 6
43 DIF_6#
GND 7
VDDR 8
DIF_IN 9
DIF_IN# 10
vSMB_A0_tri 11
9ZXL1251
connect epad (pin 65)
to ground
42 DIF_6
41 GND
40 VDD
39 DIF_5#
38 DIF_5
SMBDAT 12
37 vOE5#
SMBCLK 13
36 vOE4#
vSMB_A1_tri 14
DFB_OUT_NC# 15
35 DIF_4#
34 DIF_4
DFB_OUT_NC 16
33 GND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
9 x 9mm VFQFPN package
Note: Pins with ^ prefix have internal 120K pullup
Pins with v prefix have internal 120K pulldowm
Pins with ^v prefix have internal 120K pullup/pulldown (biased to VDD/2)
Power Management Table
CKPWRGD_PD#
0
1
DIF_IN/
DIF_IN#
X
Running
SMBus
EN bit
X
0
1
PLL STATE
IF NOT IN
DIF(11:0)/ BYPASS
DIF(11:0)# MODE
Low/Low
OFF
Low/Low
ON
Running
ON
Functionality at Power-up (PLL mode)
100M_133M#
1
0
DIF_IN
MHz
100.00
133.33
DIF(11:0)
DIF_IN
DIF_IN
Power Connections
Pin Number
VDD
1
8
24,40,57
VDDIO
25,32,49,56
GND
2
7
23,33,41,48,
58,65
Description
Analog PLL
Analog Input
DIF clocks
12-OUTPUT DB1200ZL DERIVATIVE WITH INTEGRATED 85Ω TERMINATIONS 2
REVISION B 11/20/15
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