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841N254B 반도체 회로 부품 판매점

NG Crystal-to-LVDS/ HCSL Clock Synthesizer



IDT 로고
IDT
841N254B 데이터시트, 핀배열, 회로
FemtoClock® NG Crystal-to-LVDS/ HCSL
Clock Synthesizer
841N254B
Datasheet
General Description
The 841N254B is a 4-output clock synthesizer designed for S-RIO
1.3 and 2.0 reference clock applications. The device generates four
copies of a selectable 250MHz, 156.25MHz, 125MHz or 100MHz
clock signal with excellent phase jitter performance. The four outputs
are organized in two banks of two LVDS and two HCSL ouputs.The
device uses IDT’s fourth generation FemtoClock® NG technology for
an optimum of high clock frequency and low phase noise
performance, combined with a low power consumption and high
power supply noise rejection. The synthesized clock frequency and
the phase-noise performance are optimized for driving RIO 1.3 and
2.0 SerDes reference clocks. The device supports 3.3V and 2.5V
voltage supplies and is packaged in a small 32-lead VFQFN
package. The extended temperature range supports wireless
infrastructure, telecommunication and networking end equipment
requirements.
Function Table
Inputs
F_SEL1
F_SEL0
0 (default)
0 (default)
01
10
11
Output Frequency with
fXTAL = 25MHz
156.25MHz
125MHz
100MHz
250MHz
NOTE: F_SEL[1:0] are asynchronous controls.
Block Diagram
Features
Fourth generation FemtoClock® (NG) technology
Selectable 250MHz, 156.25MHz, 125MHz or 100MHz output
clock synthesized from a 25MHz fundamental mode crystal
Four differential clock outputs (two LVDS and two HCSL outputs)
Crystal interface designed for 25MHz,
parallel resonant crystal
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1MHz - 20MHz): 0.27ps (typical)
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(12kHz - 20MHz): 0.32ps (typical)
Power supply noise rejection PSNR: -50dB (typical)
LVCMOS interface levels for the frequency select input
Full 3.3V or 2.5V supply voltage
Lead-free (RoHS 6) packaging
-40°C to 85°C ambient operating temperature
Pin Assignment
32 31 30 29 28 27 26 25
VDD 1
24 IREF
nc 2
VDDA 3
nc 4
841N254B
32-lead VFQFN
K Package
23 GND
22 nQA0
21 QA0
GND 5 5mm x 5mm x 0.925mm 20 VDDOA
package body
REF_CLK 6
Top View
19 nQA1
nOEA 7
18 QA1
VDD 8
17 GND
9 10 11 12 13 14 15 16
XTAL_IN
XTAL_OUT
REF_CLK
REF_SEL
BYPASS
F_SEL[0:1]
nOEA
nOEB
IREF
OSC 0
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
1
2
PFD
&
LPF
FemtoClock® NG
VCO
625MHz
1
÷N
0
÷25
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
LVDS
LVDS
HCSL
HCSL
©2016 Integrated Device Technology, Inc..
1
Revision B, May 23, 2016


841N254B 데이터시트, 핀배열, 회로
841N254B Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1, 8, 13, 32
2, 4
3
5, 17,
23, 25, 31
6
7
Name
VDD
nc
VDDA
GND
REF_CLK
nOEA
Type
Power
Unused
Power
Description
Core supply pins.
No connect.
Analog power supply.
Power
Power supply ground.
Input
Input
Pulldown Alternative single-ended reference clock input. LVCMOS/LVTTL interface levels.
Pulldown Output enable input. See Table 3D for function. LVCMOS/LVTTL interface levels.
9
nOEB
Input
Pulldown Output enable input. See Table 3E for function. LVCMOS/LVTTL interface levels.
10
REF_SEL
Input
Pulldown Reference select input. See Table 3B for function.
LVCMOS/LVTTL interface levels.
11,
12
XTAL_IN,
XTAL_OUT
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
14
BYPASS
Input
Pulldown Bypass mode select pin. See Table 3C for function.
LVCMOS/LVTTL interface levels.
15,
16
F_SEL0,
F_SEL1
Input
Pulldown Frequency select pin. See Table 3A for function. LVCMOS/LVTTL interface levels.
18, 19
20
21, 22
24
QA1, nQA1
VDDOA
QA0, nQA0
IREF
Output
Power
Output
Input
Differential clock output. LVDS interface levels.
Output supply pin for QAx outputs.
Differential clock output. LVDS interface levels.
External fixed precision resistor (475) from this pin to ground provides a reference
current used for differential current-mode QBx, nQBx clock outputs.
26, 27
28
29, 30
nQB1, QB1
VDDOB
nQB0, QB0
Output
Power
Output
Differential clock output. HCSL interface levels.
Output supply pin for QBx outputs.
Differential clock output. HCSL interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN Input Capacitance
RPULLDOWN Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
100
Maximum
Units
pF
k
©2016 Integrated Device Technology, Inc.
2
Revision B, May 23, 2016




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841N254B

NG Crystal-to-LVDS/ HCSL Clock Synthesizer - IDT