파트넘버.co.kr 9DBU0241 데이터시트 PDF


9DBU0241 반도체 회로 부품 판매점

2 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB



IDT 로고
IDT
9DBU0241 데이터시트, 핀배열, 회로
2 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
w/Zo=100ohms
9DBU0241
DATASHEET
Description
The 9DBU0241 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. It has integrated output terminations
providing Zo=100ohms for direct connection to 100ohm
transmission lines. The device has 2 output enables for clock
management.
Recommended Application
1.5V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB)
Output Features
2 – 1-167MHz Low-Power (LP) HCSL DIF pairs
w/ZO=100
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
DIF bypass mode additive phase jitter is <300fs rms for
PCIe Gen3
DIF bypass mode additive phase jitter <350fs rms for
12k-20MHz
Block Diagram
Features/Benefits
Direct connection to 100transmission lines; saves 8
resistors compared to standard HCSL outputs
35mW typical power consumption in PLL mode; eliminates
thermal concerns
Spread Spectrum (SS) compatible; allows SS for EMI
reduction
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
SMBus-selectable features; optimize signal integrity to
application
slew rate for each output
differential output amplitude
Pin/SMBus selectable PLL bandwidth and PLL Bypass;
optimize PLL to application
Outputs blocked until PLL is locked; clean system start-up
Device contains default configuration; SMBus interface not
required for device control
3.3V tolerant SMBus interface works with legacy controllers
Space saving 24-pin 4x4mm VFQFPN; minimal board
space
vOE(1:0)#
2
CLK_IN
CLK_IN#
SS-
Compatible
PLL
DIF1
DIF0
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
9DBU0241 REVISION C 04/22/15 1 ©2015 Integrated Device Technology, Inc.


9DBU0241 데이터시트, 핀배열, 회로
9DBU0241 DATASHEET
Pin Configuration
FB_DNC# 1
VDDR1.5 2
CLK_IN 3
CLK_IN# 4
GNDR 5
GNDDIG 6
24 23 22 21 20 19
9DBU0241
epad is Gnd
7 8 9 10 11 12
18 DIF1#
17 DIF1
16 VDDA1.5
15 GNDA
14 DIF0#
13 DIF0
24-pin VFQFPN, 4x4 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
^v prefix indicates internal 120KOhm pull up AND
pull down resistor (biased to VDD/2)
v prefix indicates internal 120KOhm pull down
resistor
SMBus Address Selection Table
Address
1101101
+ Read/Write bit
x
Power Management Table
CKPWRGD_PD#
0
CLK_IN
X
SMBus
OEx bit
X
OEx# Pin
X
DIFx
True O/P Comp. O/P
Low Low
1
Running
0
X
Low Low
1
Running
1
0
Running
Running
1
Running
1
1
Low Low
1. If Bypass mode is selected, the PLL will be off, and outputs will be running.
PLL
Off
On1
On1
On1
Power Connections
Pin Number
VDD
GND
Description
2 5 Input receiver analog
7 6 Digital Power
11,20
10,21
DIF outputs
16 15 PLL Analog
Note: epad on this device is not electrically connected to the die.
It should be connected to ground for best thermal performance.
PLL Operating Mode
HiBW_BypM_LoBW#
0
M
1
MODE
PLL Lo BW
Bypass
PLL Hi BW
Byte1 [7:6]
Readback
00
01
11
Byte1 [4:3]
Control
00
01
11
2 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
2
REVISION C 04/22/15




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9DBU0241

2 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB - IDT