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9FGP204 반도체 회로 부품 판매점

FREQUENCY TIMING GENERATOR



IDT 로고
IDT
9FGP204 데이터시트, 핀배열, 회로
DATASHEET
Frequency Timing Generator for Peripherals
9FGP204
Recommended Application:
Peripheral Clock for Intel Server
Output Features:
• 1 - 0.7V current-mode differential CPU pair
• 6 - 50MHz RMII outputs
• 2 - 125MHz RGMII outputs
• 1 - DOT 96MHz output
• 1 - 33.33MHz output
• 1 - 32.768KHz output
• 2 - 25MHz REF outputs
Key Specifications:
• Exact synthesis on CPU, RGMII, RMII & 33.33MHz
clocks
• +/- 100ppm frequency accuracy on other clocks
Features/Benefits:
• Selectable SMBus Address - D0/D1 or C0/C1
• Spread Spectrum capability on CPU and DOT 96MHz
clocks
• SMBus Control:
- M/N and spread programming on CPU and DOT
96MHz clocks via SMBus
- Differential outputs can be disabled via pins or SMBus
Pin Configuration
40 39 38 37 36 35 34 33 32 31
GND 1
30 GNDRMII
VDD96 2
29 RMII2
DOT96SST 3
28 RMII3
DOT96SSC 4
27 GNDRMII
OE_96 5
OE_CPU 6
9FGP204
26 VDDRMII
25 RMII4
CPUCLKT0 7
24 RMII5
CPUCLKC0 8
23 VDD33
VDDCPU 9
22 33.33MHZ/**SMBADR
GNDCPU 10
21 GND33
11 12 13 14 15 16 17 18 19 20
40-MLF
* Internal Pull-Up Resistor
** Internal Pull-Dow n Resistor
Functionality
CPU FS2 CPU FS1 CPU FS0 CPUCLK DOT96SS
Byte0 Bit2 Byte0 Bit1 Byte0 Bit0 MHz
MHz
0 0 0 266.67 96.00
0 0 1 133.33 96.00
0 1 0 200.00 96.00
0 1 1 166.67 96.00
1 0 0 333.33 96.00
1 0 1 100.00 96.00
1 1 0 400.00 96.00
1 1 1 Reserved 96.00
Power up default is highlighted.
33.33
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
RMII
MHz
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
RGMII
MHz
125.00
125.00
125.00
125.00
125.00
125.00
125.00
125.00
25
MHz
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
32.768
KHz
32.768
32.768
32.768
32.768
32.768
32.768
32.768
32.768
SMBus Address Selection
SMBADR
*SMBADR = 0 SMBADR = 1
D0/D1
C0/C1
* Default value
IDT® Frequency Timing Generator for Peripherals
1
1604B—08/29/11


9FGP204 데이터시트, 핀배열, 회로
9FGP204
Frequency Timing Generator for Peripherals
Pin Description
PIN #
PIN NAME
1 GND
2 VDD96
3 DOT96SST
4 DOT96SSC
5 OE_96
6 OE_CPU
7 CPUCLKT0
8 CPUCLKC0
9 VDDCPU
10 GNDCPU
11 IREF
12 VDD32K
13 32.768KHz
14 GND32K
15 VDDREF
16 25MHz_0
17 25MHZ_1
18 GNDREF
19 X1_25
20 X2_25
21 GND33
22 33.33MHZ/**SMBADR
23 VDD33
24 RMII5
25 RMII4
26 VDDRMII
27 GNDRMII
28 RMII3
29 RMII2
30 GNDRMII
31 VDDRMII
32 RMII1
33 RMII0
34 VDDRGMII
35 GNDRGMII
36 RGMII1
37 RGMII0
38 SMBCLK
39 SMBDAT
40 VttPwr_GD/PD#
PIN
TYPE
PWR
PWR
OUT
OUT
IN
IN
OUT
OUT
PWR
PWR
OUT
PWR
OUT
PWR
PWR
OUT
OUT
PWR
IN
OUT
PWR
I/O
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
IN
I/O
IN
DESCRIPTION
Ground pin.
Power pin for the DOT96 clocks, nominal 3.3V
True clock of differential pair for 96.00MHz spread spectrum capable DOT clock. These are
current mode outputs. External resistors are required for voltage bias.
Complementary clock of differential pair for 96.00MHz spread spectrum capable DOT clock.
These are current mode outputs. External resistors are required for voltage bias.
Active high input for enabling 96Hz outputs.
1 = enable output(s), 0 =disable output(s)
Active high input for enabling CPU DIFF pairs.
1 = enable output(s), 0 =disable output(s)
True clock of differential pair CPU outputs. These are current mode outputs. External resistors
are required for voltage bias.
Complementary clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Ground pin for the CPU outputs
This pin establishes the reference for the differential current-mode output pairs. It requires a
fixed precision resistor to ground. 475ohm is the standard value for 100ohm differential
impedance. Other impedances require different values. See data sheet.
Power pin for the 32.768KHz outputs, nominal 3.3V
32.768KHz clock output
Ground pin for the 32.768KHz outputs
Ref, XTAL power supply, nominal 3.3V
25MHz clock output, 3.3V
25MHz clock output, 3.3V
Ground pin for the REF outputs.
Crystal input, Nominally 25.00MHz.
Crystal output.
Ground pin for the 33.33MHz outputs
33.33MHz clock output / SMBus address select bit.
Power pin for the 33.33MHz outputs, nominal 3.3V
3.3V 50MHz RMII clock output
3.3V 50MHz RMII clock output
3.3V power pin for the RMII clocks.
Ground pin for the RMII outputs
3.3V 50MHz RMII clock output
3.3V 50MHz RMII clock output
Ground pin for the RMII outputs
3.3V power pin for the RMII clocks.
3.3V 50MHz RMII clock output
3.3V 50MHz RMII clock output
3.3V power pin for the RGMII clocks and PLL
Ground pin for the RGMII outputs
3.3V 125MHz RGMII clock output
3.3V 125MHz RGMII clock output
Clock pin of SMBUS circuitry, 5V tolerant
Data pin of SMBUS circuitry, 5V tolerant
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid
and are ready to be sampled. This is an active high input. / Asynchronous active low input pin
used to power down the device into a low power state.
IDT® Frequency Timing Generator for Peripherals
2
1604B—08/29/11




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