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PDF AP0101CS Data sheet ( Hoja de datos )
| Número de pieza | AP0101CS | |
| Descripción | High-Dynamic Range (HDR) Image Signal Processor | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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AP0101CS HDR: Image Signal Processor (ISP)
Features
AP0101CS High-Dynamic Range (HDR)
Image Signal Processor (ISP)
AP0101CS Datasheet, Rev. 7
For the latest product datasheet, please visit www.onsemi.com
Features
• Supports ON Semiconductor sensors with up to
1.2 Mp (1280x960)
• 45 fps at 1.2 Mp, 60 fps at 720p
• Optimized for operation with HDR sensors
• Color and gamma correction
• Auto exposure, auto white balance, 50/60 Hz flicker
avoidance
• Adaptive Local Tone Mapping (ALTM)
• Test Pattern Generator
• Two-wire serial programming interface
• Interface to low-cost Flash or EPROM through SPI
bus (to configure and load patches)
• High-level host command interface
• Standalone operation supported
• Up to 5 GPIO
• Fail-safe IO
• Multi-Camera synchronization support
• Dual Band IR filter support
Applications
• SMPTE296 HDCCTV cameras
• Surveillance network IP cameras
Table 1:
Key Performance Parameters
Parameter
Value
Primary camera
interface
Parallel
Primary camera input
format
Output interface
RAW12 Linear/Companded Bayer
data
Up to 20-bit Parallel1
Output format
YUV422 8-bit,10-bit, and
SMPTE296M
10-, 12-bit tone-mapped Bayer
Maximum resolution 1280x960 (1.2 Mp)
Input clock range2
6-30 MHz
Maximum frame rate3 45 fps at 1.2 Mp, 60 fps at 720p
Maximum output clock
frequency
Parallel clock up to 84 MHz
VDDIO_S 1.8 or 2.8 V nominal
Supply VDDIO_H
voltage VDD_REG
2.5 or 3.3 V nominal
1.8V nominal
VDDIO_OTPM 2.5 or 3.3 V nominal
Operating temperature
(ambient - TA)
–30°C to +70°C
Typical power
consumption4
130 mW
Notes: 1. 20-bit in one pixel clock format is only available in
SMPTE mode with the use of 4 GPIOs.
2. With input clock below 10 MHz, the two wire
serial interface is supported only up to 100 KHz
3. Maximum frame rate depends on output inter-
face and data format configuration used.
4. 720p HDR 60 fps 74.25 MHz YCbCr_422_16
AP0101CS/D Rev. 7, 1/16 EN
1 ©Semiconductor Components Industries, LLC 2016,
1 page  
AP0101CS HDR: Image Signal Processor (ISP)
System Interfaces
Figure 2: Typical Configuration
S ensor IO
power
1.8V
(R e g u la to r
IP)
1.2V (R egulator OP)
P ower up C ore and
PLL
OTPM
Power
Host IO
power
RPULL-UP2
VDDIO _S
VDD _REG FB _SENSE LDO_O P VDD _PLL VDD
M_S CLK
M_S DATA
EXTCLK_OUT
RESET_BAR_OUT
F V _IN
LV_IN
PIXCLK _IN
DIN [11:0]
TRIGGER_OUT
G ND_REG
GND
VDDIO _H
S CLK
RESET_BAR3
S DATA
S ADDR
FRAME_SYNC
EXTCLK
XTAL
STANDBY
FV_OUT
LV_OUT
PIXCLK_OUT
DOUT [15:0]
S P I_CS_BAR
SPI_CLK
SPI_SDO
SPI_SDI
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
TRST_BAR5
RPULL-UP2
Oscillator
VDDIO_S6 VDD_REG4 LDO_OP4
VDDIO_OTPM VDDIO_H6
Notes:
1. This typical configuration shows only one scenario out of multiple possible variations for this sen-
sor.
2. ON Semiconductor recommends a 1.5kresistor value for the two-wire serial interface RPULL-UP;
however, greater values may be used for slower transmission speed.
3. RESET_BAR has an internal pull-up resistor and can be left floating if not used.
4. The decoupling capacitors for the regulator input and output should have a value of 1.0uF. The
capacitors should be ceramic and need to have X5R or X7R dielectric.
5. TRST_BAR connects to GND for normal operation.
6. ON Semiconductor recommends that 0.1F and 1F decoupling capacitors for each power supply
are mounted as close as possible to the pin. Actual values and numbers may vary depending on lay-
out and design consideration
AP0101CS/D Rev. 7, 1/16 EN
5 ©Semiconductor Components Industries, LLC,2016.
5 Page 
AP0101CS HDR: Image Signal Processor (ISP)
System Interfaces
Table 7:
Output States
Hardware States
Firmware States
Name
Reset State Default State Hard Standby Soft Standby Streaming
Idle Notes
SPI_SCLK
High-
impedance
driven, logic 0 driven, logic 0 driven, logic 0
Output
SPI_SDI
Internal pull- Internal pull- Internal pull- internal pull-
up enabled up enabled up enabled up enabled
Input. Internal pull-
up permanently
enabled.
SPI_SDO
High-
impedance
driven, logic 0 driven, logic 0 driven, logic 0
Output
SPI_CS_BAR
High-
impedance
driven, logic 1 driven, logic 1 driven, logic 1
Output
EXT_CLK_OUT
driven, logic
0
driven, logic 0 driven, logic 0 driven, logic 0
Output
RESET_BAR_O driven, logic
UT 0
driven, logic 0 driven, logic 1 driven, logic 1
Output. Firmware
will release sensor
reset
M_SCLK
High-
High-
impedance impedance
High-
impedance
High-
impedance
Input/Output. A
valid logic level
should be
established by pull-
up
M_SDATA
High-
High-
impedance impedance
High-
impedance
High-
impedance
Input/Output. A
valid logic level
should be
established by pull-
up
FV_IN ,LV_IN,
PIXCLK_IN, n/a
n/a
n/a
n/a
DIN[11:0]
Input. Must always
n/a be driven to a valid
logic level
FV_OUT,
LV_OUT,
PIXCLK_OUT,
DOUT[15:0]
High-
impedance
Varied
Output. Default
Driven if used Driven if used Driven if used Driven if used state dependent on
configuration
GPIO[5:2]
High-
impedance
Input, then
high-
impedance
Driven if used
Driven if used
Driven if used
Driven if used
Input/Output. After
reset these pins are
sampled as inputs as
part of auto-
configuration.
GPIO1
High-
High-
impedance impedance
High-
impedance
High-
impedance
High-
impedance
High-
impedance
TRIGGER_OUT
High-
impedance
High-
impedance
Driven if used Driven if used Driven if used Driven if used
TRST_BAR
n/a
n/a
(negated)
(negated)
(negated)
(negated)
Input. Must always
be driven to a valid
logic level.
AP0101CS/D Rev. 7, 1/16 EN
11
©Semiconductor Components Industries, LLC,2016.
11 Page | ||
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