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PDF BGS15MA12 Data sheet ( Hoja de datos )
| Número de pieza | BGS15MA12 | |
| Descripción | SP5T Rx Diversity Switch | |
| Fabricantes | Infineon | |
| Logotipo |  |
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BGS15MA12
SP5T Rx Diversity Switch
Data Sheet
Revision 3.1 - 2016-05-11
Power Management & Multimarket
1 page  
BGS15MA12 SP5T Rx Diversity Switch
1 Features
• Low insertion loss
• Low harmonic generation
• High port-to-port-isolation
• Suitable for LTE / WCDMA Rx Applications
• 0.1 to 2.9 GHz coverage
• No decoupling capacitors required if no DC applied on RF lines
• On chip control logic including ESD protection
• Integrated MIPI RFFE interface operating in 1.1 to 1.95 V voltage
range
• Software programmable MIPI RFFE USID
• Direct to battery supply
• Small form factor 1.1 mm x 1.9 mm
• No power supply blocking required
• High EMI robustness
• RoHS and WEEE compliant package
BGS15MA12
2 Product Description
The BGS15MA12 RF MOS switch is specifically designed for LTE and WCDMA diversity applications. This SP5T
offers low insertion loss and low harmonic generation in termination mode.
The switch is controlled via a MIPI RFFE controller. The on-chip controller allows power-supply voltages from
1.1 to 1.95 V. The switch features direct-connect-to-battery functionality and DC-free RF ports. Unlike GaAs tech-
nology, external DC blocking capacitors at the RF Ports are only required if DC voltage is applied externally. The
BGS15MA12 RF Switch is manufactured in Infineon’s patented MOS technology, offering the performance of GaAs
with the economy and integration of conventional CMOS including the inherent higher ESD robustness. The device
has a very small size of only 1.1 x 1.9 mm2 and a maximum height of 0.65 mm.
Table 1: Ordering Information
Type
Package
BGS15MA12
ATSLP-12-4
Data Sheet
Marking
S4
5
Chip
m4829
Revision 3.1 - 2016-05-11
5 Page 
BGS15MA12
6 MIPI RFFE Specification
All sequences are implemented according to the ’MIPI Alliance Specification for RF Front-End Control Interface’
document version 1.10 - 26. July 2011.
Table 7: MIPI Features
Feature
Register write command sequence
Register read command sequence
Extended register write command sequence
Extented register read command sequence
Register 0 write command sequence
Trigger function
Supported
Yes
Yes
No
No
Yes
Yes
Programmable USID
Yes
Status Register
Reset
Group SID
SSEL1 and SSEL2 pins
Yes
Yes
Yes
Yes
Full speed write
Half speed read
Full speed read
Yes
Yes
Yes
Comment
Up to 4 Bytes
Up to 4 Bytes
Trigger assignment to each control register is sup-
ported
3 register command sequence and extended regis-
ter command sequence
Register for debugging
By VIO, Power Mode and RFFE_STATUS
External pins for changing USID:
SSEL1=0 & SSEL2=0 → 1000,
SSEL1=0 & SSEL2=1 → 1001,
SSEL1=1 & SSEL2=0 → 1010,
SSEL1=1 & SSEL2=1 → 1011
Table 8: Startup Behavior
Feature
Power status
Trigger function
State
LOW POWER
ENABLED
Comment
The chip is in low power mode after startup
Trigger function is enabled after startup. Trigger function can be dis-
abled via PM_TRIG register.
Data Sheet
11 Revision 3.1 - 2016-05-11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet BGS15MA12.PDF ] | |
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