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Megawin Technology |
MEGAWIN
MAKE YOU WIN
MG103
数据手册
版本 1.05
MG103
This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
1/62
MEGAWIN
MAKE YOU WIN
MG103
目录
1. 概述 ..............................................................................................................4
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2. 功能 ..............................................................................................................5
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3. 引脚 ..............................................................................................................6
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3.1. 封装 .......................................................................................................................................6
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3.2. 引脚定义 ................................................................................................................................7
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4. 方框图...........................................................................................................8
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5. 特殊功能寄存器SFR .....................................................................................9
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5.1. SFR 映射表...........................................................................................................................9
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5.2. SFR 位分配.........................................................................................................................10
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6. 8051 CPU 功能描述...................................................................................11
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6.1. CPU 寄存器 ........................................................................................................................11
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6.2. CPU 时序............................................................................................................................12
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6.3. CPU 寻址方式.....................................................................................................................12
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7. 存储器结构..................................................................................................13
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7.1. 片上程序存储器 ...................................................................................................................14
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7.2. 片上数据存储器 RAM .........................................................................................................15
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7.3. 关于C51 编译器的声明识别符 .............................................................................................16
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8. 双数据指针寄存器 (DPTR) .........................................................................17
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9. I/O 结构......................................................................................................18
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9.1. IO 配置................................................................................................................................18
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9.1.1. 准双向口........................................................................................................................18
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9.1.2. 推挽输出........................................................................................................................18
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9.1.3. 仅输入(高阻输入) ..........................................................................................................19
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9.1.4. 开漏集输出 ....................................................................................................................19
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9.2. I/O 端口寄存器....................................................................................................................20
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9.2.1. 端口 1 ...........................................................................................................................21
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9.2.2. 端口 3 ...........................................................................................................................21
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10. 中断 ............................................................................................................22
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10.1. 中断结构 ..............................................................................................................................22
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10.2. 中断寄存器 ..........................................................................................................................23
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11. 定时器/计数器 .............................................................................................26
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11.1. 定时器 0 和定时器 1............................................................................................................26
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11.1.1. 模式 0 ...........................................................................................................................26
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11.1.2. 模式 1............................................................................................................................27
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11.1.3. 模式 2............................................................................................................................27
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11.1.4. 模式 3............................................................................................................................28
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11.1.5. 定时器时钟输出.............................................................................................................28
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11.1.6. 定时器 0/1 寄存器..........................................................................................................29
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12. 串行口 (UART)...........................................................................................31
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12.1. 帧错误检测 ..........................................................................................................................31
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12.2. 多处理器通讯.......................................................................................................................32
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12.3. 自动地址识别.......................................................................................................................32
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This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
2/62
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